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CS43131 Datasheet(PDF) 76 Page - Cirrus Logic |
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CS43131 Datasheet(HTML) 76 Page - Cirrus Logic |
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76 / 156 page  76 DS1155F1 CS43131 5.13 Example Sequences 5.13.2 Power-Up Sequence to DSD Playback In Ex. 5-8, a 22.5792-MHz crystal is used, the PLL is used to create a 24.576-MHz MCLK, XSP is set as DSD slave at 2.8224 MHz, and full-scale output is 1.732 Vrms. 28 Headphone detect HP Detect. 0xD0000 0xC4 HPDETECT_CTRL HPDETECT_INV HPDETECT_RISE_DBC_TIME HPDETECT_FALL_DBC_TIME Reserved 11 0 0 0 10 0 HP detect enabled HP detect input is not inverted Tip sense rising debounce time set to 0 ms Tip sense falling debounce time set to 500 ms 29 Enable interrupts 30 Read Interrupt Status 1 register (0xF0000) and Interrupt Status 2 register (0xF0001) to clear sticky bits. 31 Enable headphone detect interrupts Interrupt Mask 1. 0xF0010 0x87 DAC_OVFL_INT_MASK HPDETECT_PLUG_INT_MASK HPDETECT_UNPLUG_INT_MASK XTAL_READY_INT_MASK XTAL_ERROR_INT_MASK PLL_READY_INT_MASK PLL_ERROR_INT_MASK PDN_DONE_INT_MASK 1 0 0 0 0 1 1 1 Enable HPDETECT_PLUG interrupt Enable HPDETECT_UNPLUG interrupt 32 Enable ASP interrupts Interrupt Mask 2. 0xF0011 0x07 ASP_OVFL_INT_MASK ASP_ERROR_INT_MASK ASP_LATE_INT_MASK ASP_EARLY_INT_MASK ASP_NOLRCK_INT_MASK Reserved 0 0 0 0 0 111 Enable ASP_OVFL interrupt Enable ASP_ERROR interrupt Enable ASP_LATE interrupt Enable ASP_EARLY interrupt Enable ASP_NOLRCK interrupt 33 Wait for interrupt. Check if XTAL_READY_INT = 1 in Interrupt Status 1 register (0xF0000). 34 Switch MCLK source to XTAL System Clocking Control 1. 0x10006 0x04 Reserved MCLK_INT MCLK_SRC_SEL 0000 0 1 00 MCLK Source set to XTAL. MCLK_INT frequency set to 22.5792 MHz 35 Wait at least 150 µs. 36 Enable ASP clocks Pad Interface Configuration. 0x1000D 0x02 Reserved XSP_3ST ASP_3ST 0000 00 1 0 XSP Interface status is don't care (set to default) Enable serial clocks in Master Mode 37 Power up HP Refer to Ex. 5-5 for PCM power-up sequence Example 5-8. Startup to DSD Playback STEP TASK REGISTER/BIT FIELDS VALUE DESCRIPTION 1 Apply all relevant power supplies, then assert RESET. 2 Wait for 1.5 ms. 3 Configure XTAL driver 4 Configure XTAL bias current strength (assuming River Crystal at 22.5792 MHz) Crystal Setting. 0x20052 0x04 Reserved XTAL_IBIAS 0000 0 100 Bias current set to 12.5 µA 5 Read Interrupt Status 1 register (0xF0000) to clear any pending interrupts. 6 Enable XTAL interrupts Interrupt Mask 1. 0xF0010 0xE7 DAC_OVFL_INT_MASK HPDETECT_PLUG_INT_MASK HPDETECT_UNPLUG_INT_MASK XTAL_READY_INT_MASK XTAL_ERROR_INT_MASK PLL_READY_INT_MASK PLL_ERROR_INT_MASK PDN_DONE_INT_MASK 1 1 1 0 0 1 1 1 Enable XTAL_READY interrupt Enable XTAL_ERROR interrupt 7 Start XTAL Power Down Control. 0x20000 0xF6 PDN_XSP PDN_ASP PDN_DSDIF PDN_HP PDN_XTAL PDN_PLL PDN_CLKOUT Reserved 1 1 1 1 0 1 1 0 Power up XTAL driver Example 5-7. Startup to I2S Playback (Cont.) STEP TASK REGISTER/BIT FIELDS VALUE DESCRIPTION |
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