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CS43131 Datasheet(PDF) 97 Page - Cirrus Logic |
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CS43131 Datasheet(HTML) 97 Page - Cirrus Logic |
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97 / 156 page  DS1155F1 97 CS43131 5.13 Example Sequences 25 Configure Class H Amplifier Class H Control. 0xB0000 0x1E Reserved ADPT_PWR HV_EN EXT_VCPFILT 000 111 1 0 Output Signal determines voltage level High Voltage Mode enabled Using Internal VCPFILT source. 26 Set HP output to full scale HP Output Control 1. 0x80000 0x30 HP_CLAMPA HP_CLAMPB OUT_FS HP_IN_EN HP_IN_LP Reserved +1dB_EN 0 0 11 0 0 0 0 Set HP output to Full Scale (1.732 Vrms) 27 Headphone Detect HP Detect. 0xD0000 0xC4 HPDETECT_CTRL HPDETECT_INV HPDETECT_RISE_DBC_TIME HPDETECT_FALL_DBC_TIME Reserved 11 0 00 10 0 HP detect enabled HP detect input is not inverted Tip Sense rising debounce time set to 0 ms Tip sense falling debounce time set to 500 ms 28 Enable Interrupts 29 Read Interrupt Status 1 register (0xF0000), Interrupt Status 2 register (0xF0001) and Interrupt Status 5 register (0xF0004) to clear sticky bits 30 Enable Headphone Detect Interrupts Interrupt Mask 1. 0xF0010 0x99 DAC_OVFL_INT_MASK HPDETECT_PLUG_INT_MASK HPDETECT_UNPLUG_INT_MASK XTAL_READY_INT_MASK XTAL_ERROR_INT_MASK PLL_READY_INT_MASK PLL_ERROR_INT_MASK PDN_DONE_INT_MASK 1 0 0 1 1 0 0 1 DAC_OVFL_INT is don’t care Unmask HPDETECT_PLUG interrupt Unmask HPDETECT_UNPLUG interrupt XTAL_READY_INT is don’t care XTAL_ERROR_INT is don’t care PLL_READY Interrupt is already unmasked PLL_ERROR Interrupt is already unmasked PDN_DONE_INT is don’t care 31 Enable XSP Interrupts Interrupt Mask 2. 0xF0011 0x07 XSP_OVFL_INT_MASK XSP_ERROR_INT_MASK XSP_LATE_INT_MASK XSP_EARLY_INT_MASK XSP_NOLRCK_INT_MASK Reserved 0 0 0 0 0 111 Enable XSP_OVFL interrupt Enable XSP_ERROR interrupt Enable XSP_LATE interrupt Enable XSP_EARLY interrupt Enable XSP_NOLRCK interrupt 32 Enable DSD and DoP Interrupts Interrupt Mask 5. 0xF0014 0x01 DSD_STUCK_INT_MASK DSD_INVAL_A_INT_MASK DSD_INVAL_B_INT_MASK DSD_SILENCE_A_INT_MASK DSD_SILENCE_B_INT_MASK DSD_RATE_ERROR_INT_MASK DOP_MRK_DET_INT_MASK DOP_ON_INT_MASK 0 0 0 0 0 0 0 1 Enable DSD_STUCK interrupt Enable DSD_INVAL_A interrupt Enable DSD_INVAL_B interrupt Enable DSD_SILENCE_A interrupt Enable DSD_SILENCE_B interrupt Enable DSD_RATE_ERROR interrupt Enable DOP_MRK_DET interrupt Disable DOP_ON interrupt 33 Set MCLK Source and Frequency System Clocking Control. 0x10006 0x04 Reserved MCLK_INT MCLK_SRC_SEL 0000 0 1 00 MCLK Frequency is set to 22.5792 MHz MCLK Source is set to XTAL 34 Wait for at least 150 µs 35 Enable XSP Clocks Pad Interface Configuration. 0x1000D 0x01 Reserved XSP_3ST ASP_3ST 0000 00 0 1 ASP Interface status is don’t care (set to default) Enable XSP serial clocks in master mode 36 Enable XSP and CLKOUT Power Down Control. 0x20000 0x74 PDN_XSP PDN_ASP PDN_DSDIF PDN_HP PDN_XTAL PDN_PLL PDN_CLKOUT Reserved 0 1 1 1 0 1 0 0 Enable XSP Data pins and CLKOUT XTAL is already enabled 37 Apply the DSD Power-up Sequence in Ex. 5-6. Note that in Step 1 of Ex. 5-6, use HH = 7F for DoP over XSP interface. 38 Enable ASP 39 Set ASP sample rate Serial Port Sample Rate. 0x1000B 0x01 Reserved ASP_SPRATE 0000 0001 Set sample rate to 44.1 kHz Example 5-18. DoP and PCM Mixing (Cont.) STEP TASK REGISTER/BIT FIELDS VALUE DESCRIPTION |
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