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CS43131 Datasheet(PDF) 87 Page - Cirrus Logic |
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CS43131 Datasheet(HTML) 87 Page - Cirrus Logic |
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87 / 156 page  DS1155F1 87 CS43131 5.13 Example Sequences 5.13.6 Power-Up Sequence to DoP Playback with PLL in Mono Mode In Ex. 5-9, an external 19.2-MHz MCLK is used with a PLL to generate an internal MCLK or 22.5792 MHz, and the ASP is in clock master receiving DoP data with LRCLK at 176.4 kHz and SCLK at 8.4672 MHz. 35 Switch MCLK source to PLL System Clocking Control 1. 0x10006 0x01 Reserved MCLK_INT MCLK_SRC_SEL 0000 0 0 01 MCLK Source set to PLL. MCLK_INT frequency set to 24.576 MHz 36 Wait at least 150 µs. 37 Power up HP Refer to Ex. 5-6 for DSD power-up sequence. Note that in Step 1 of Ex. 5-6, use HH = DF for the DSD interface. Example 5-12. DoP Playback with PLL in Mono Mode STEP TASK REGISTER/BIT FIELDS VALUE DESCRIPTION 1 Apply all relevant power supplies, then assert RESET. 2 Wait for 1.5 ms. 3 Configure PLL. XTI/MCLK input coming from an external 19.2 MHz source with PLL output set to 22.5792 MHz. Refer to Section 4.7.2 for register settings for other frequency combinations 4 Power up PLL Power Down Control. 0x20000 0xFA PDN_XSP PDN_ASP PDN_DSDIF PDN_HP PDN_XTAL PDN_PLL PDN_CLKOUT Reserved x x x x x 0 x 0 Power up PLL block 5 Set PLL Predivide value PLL Setting 9. 0x40002 0x03 Reserved PLL_REF_PREDIV 0000 00 11 Set PLL predivide value to 8 6 Set PLL output divide PLL Setting 6. 0x30008 0x08 PLL_OUT_DIV 0x08 Set PLL output divide value to 8 7 Set Fractional portion of PLL Divide Ratio PLL Setting 2. 0x30002 0x00 PLL_DIV_FRAC_0 0x00 Set LSB of PLL fractional divider value to 0 PLL Setting 3. 0x30003 0x00 PLL_DIV_FRAC_1 0x00 Set Middle Byte of PLL fractional divider value to 0 PLL Setting 4. 0x30004 0x80 PLL_DIV_FRAC_2 0x80 Set MSB of PLL fractional divider value to 0x80 8 Set Integer portion of PLL Divide Ratio PLL Setting 5. 0x30005 0x49 PLL_DIV_INT 0x49 Set PLL integer Divide value to 0x49 9 Set PLL mode PLL Setting 8. 0x3001B 0x01 Reserved PLL_MODE Reserved 0000 00 0 1 500/512 factor is used in PLL frequency calculation 10 Read Interrupt Status 1 register (0xF0000) to clear sticky bits. 11 Set PLL calibration ratio PLL Setting 7. 0x3000A 0x97 PLL_CAL_RATIO 0x97 PLL Calibration Ratio is set to 0x97 (151) 12 Enable PLL interrupts Interrupt Mask 1. 0xF0010 0xF9 DAC_OVFL_INT_MASK HPDETECT_PLUG_INT_MASK HPDETECT_UNPLUG_INT_MASK XTAL_READY_INT_MASK XTAL_ERROR_INT_MASK PLL_READY_INT_MASK PLL_ERROR_INT_MASK PDN_DONE_INT_MASK 1 1 1 1 1 0 0 1 DAC_OVFL_INT is don't care Unmask HPDETECT_PLUG interrupt Unmask HPDETECT_UNPLUG interrupt XTAL_READY_INT is Don't Care XTAL_ERROR_INT is Don't Care PLL_READY Interrupt is already unmasked PLL_ERROR Interrupt is already unmasked PDN_DONE_INT is Don't Care 13 Start PLL PLL Setting 1. 0x30001 0x01 Reserved PLL_START 0000 000 1 Enable PLL Output 14 Playback DoP audio. Assuming 64 •Fs DSD stream 15 Configure ASP interface for DoP input 16 Set ASP sample rate Serial Port Sample Rate. 0x1000B 0x05 Reserved ASP_SPRATE 0000 0101 Set sample rate to 176.4 kHz Example 5-11. Startup to DSD Playback in Mono Mode (Cont.) STEP TASK REGISTER/BIT FIELDS VALUE DESCRIPTION |
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