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CS43131 Datasheet(PDF) 139 Page - Cirrus Logic

Part # CS43131
Description  130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver and Impedance Detection
PDF  156 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS43131 Datasheet(HTML) 139 Page - Cirrus Logic

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DS1155F1
139
CS43131
7.6 Interrupt Status and Mask Registers
6
DSD_INVAL_
A_INT_MASK
DSD_INVAL_A_INT mask.
0 Unmasked
1 (Default) Masked
5
DSD_INVAL_
B_INT_MASK
DSD_INVAL_B_INT mask.
0 Unmasked
1 (Default) Masked
4DSD_
SILENCE_A_
INT_MASK
DSD_SILENCE_A_INT mask.
0 Unmasked
1 (Default) Masked
3DSD_
SILENCE_B_
INT_MASK
DSD_SILENCE_B_INT mask.
0 Unmasked
1 (Default) Masked
2DSD_RATE_
ERROR_INT_
MASK
DSD_RATE_ERROR_INT mask.
0 Unmasked
1 (Default) Masked
1DOP_MRK_
DET_INT_
MASK
DOP_MRK_DET_INT mask.
0 Unmasked
1 (Default) Masked
0DOP_ON_
INT_MASK
DOP_ON_INT mask.
0 Unmasked
1 (Default) Masked
7.6.11 ASP Master Mode Slew Rate Control
Address 0x10 0000
R/W
76543210
—SCLK1_SLEW_RATE
—
Default
00101010
Bits
Name
Description
7:4
—
Reserved
3:2
SCLK1_
SLEW_RATE
SCLK1 slew rate control.
00 Reserved
01 Recommended drive strength for clock rate higher than 12.288 MHz
10 (Default) Recommended drive strength for clock rate 12.288 MHz or lower.
11 Reserved
1:0
—
Reserved
7.6.12 XSP Master Mode Slew Rate Control
Address 0x10 0001
R/W
76543210
—
DSDCLK_SCLK2_SLEW_RATE
—
Default
00101010
Bits
Name
Description
7:4
—
Reserved
3:2
DSDCLK_
SCLK2_
SLEW_RATE
DSDCLK/SCLK2 slew rate control.
00 Reserved
01 Recommended drive strength for clock rate higher than 12.288 MHz
10 (Default) Recommended drive strength for clock rate 12.288 MHz or lower.
11 Reserved
1:0
—
Reserved
Bits
Name
Description



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