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LTC4292 Datasheet(PDF) 34 Page - Analog Devices |
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LTC4292 Datasheet(HTML) 34 Page - Analog Devices |
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34 / 44 page  LTC9101-2/LTC9102 34 Rev. 0 For more information www.analog.com APPLICATIONS INFORMATION 9101-2 F26 C1 1µF 100V 1µF 100V 1µF 100V 1µF R1 10k 1/2W R3 10k 1/2W 1µF 47µF 100V R2 10k 1/2W R4 10k 1/2W + 1µF VEE VEE AGND CAP3 EXT3 LTC9102 VEE VEE VEE VEE VEE AGND CAP3 EXT3 CAP4 PWRIN LTC9102 C1 1µF 100V 1µF CAP4 PWRIN Figure 26. Power Supply Configuration with Internal 3.3V Supply 9101-2 F27 1µF C1 1µF 100V C2 1µF 100V R1 10k 1/2W R2 10k 1/2W 1µF 1µF 100V 1µF 100V 1µF 47µF 100V + 1µF VEE VEE 3.3V VEE VEE AGND CAP3 EXT3 PWRIN CAP4 LTC9102 VEE 3.3V AGND CAP3 EXT3 PWRIN CAP4 LTC9102 3.3V REGULATOR Figure 27. Power Supply Configuration with External 3.3V Regulators High-Speed Data Isolation The LTC9101-2/LTC9102 chipset can either provide pro- prietary isolation or rely on existing system isolation. Significant BOM cost reductions can be achieved using the proprietary isolation scheme. In the proprietary isolation scheme, the LTC9101-2/ LTC9102 chipset uses transformers to isolate the LTC9101-2 from one to four LTC9102s (see Figure 28). In this case, the SDAIN and SDAOUT pins can be shorted to each other and tied directly to the I2C/SMBus bus. The transformers should be 10Base-T or 10/100Base-T with a 1:1 turns ratio. Optimally, the selected transformers do not have common-mode chokes. These transformers typ- ically provide 1500V of isolation between the LTC9101-2 and the LTC9102s. For proper operation, strict layout guidelines must be met. In the direct connection scheme, the LTC9101-2/LTC9102 chipset relies on pre-existing system isolation. In this scheme, the LTC9101-2 connects directly to one or more LTC9102s using a proprietary communication protocol (see Figure 29). External MOSFET Careful selection of the power MOSFET is critical to sys- tem reliability. Choosing a MOSFET requires extensive analysis and testing of the MOSFET SOA curve against the various PSE current limit conditions. ADI recommends the PSMN075-100MSE for PSEs configured to deliver up to 51W maximum port power (single-signature) or 25.5W maximum pairset power (dual-signature). For PSEs configured to power up to 71.3W maximum port power (single-signature) or 35.6W maximum pairset power (dual-signature), ADI recommends the PSMN040- 100MSE. These MOSFETs are selected for their proven reliability in PoE applications. Contact ADI Applications before using a MOSFET other than one of these recom- mended parts. Sense Resistors The LTC9101-2/LTC9102 is designed for a low 0.1Ω cur- rent sense resistance per channel, laid out as shown in the Layout Requirements section, Figure 31. In order to meet the IHOLD-2P, and ILIM-2P accuracy required by the IEEE specification, the sense resistors should have ±1% |
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