LTC4292 datasheet(35/44 Pages) AD

35 / 44 page

LTC9101-2/LTC9102

Rev. 0

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APPLICATIONS INFORMATION

tolerance or better, and no more than ±200ppm/°C tem-

perature coefficient.

Port Output Cap

Each port requires a 0.1μF cap across OUTn to AGND

(see Figure 30) to keep the LTC9102 stable while in cur-

rent limit during startup or overload. Common ceramic

capacitors often have significant voltage coefficients; this

means the capacitance is reduced as the applied voltage

increases. To minimize this problem, X7R ceramic capaci-

tors rated for at least 100V are recommended and must

be located close to the LTC9102.

Surge Protection

Ethernet ports can be subject to significant cable surge

events. To keep PoE voltages below a safe level and protect

the application against damage, protection components,

as shown in Figure 30, are required at the main supply,

at the LTC9102 supply pins, and at each port.

Bulk transient voltage suppression (TVSBULK) and bulk

capacitance (CBULK) are required across the main PoE

supply and should be sized to accommodate system level

surge requirements.

Across each LTC9102 AGND pin and VEEpin is a SMAJ58A

58V TVS (D1) and a 1µF, 100V bypass capacitor (C1). These

components must be placed close to the LTC9102 pins.

Each port requires an S1B clamp diode from OUTn to

supply AGND. This diode steers harmful surges into the

supply rails where they are absorbed by the surge sup-

pressors and the VEE bypass capacitance. The layout of

these paths must be low impedance.

LTC4292 Datasheet(PDF) 35 Page - Analog Devices