LTC4292 datasheet(26/44 Pages) AD

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LTC9101-2/LTC9102

Rev. 0

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APPLICATIONS INFORMATION

The LTC9101-2/LTC9102 connects the VEE power sup-

ply to the PSE port in a controlled manner, meeting the

power demands of the PD while minimizing power dis-

sipation in the external MOSFET and disturbances to the

VEE backplane.

Inrush Control

When commanded to apply power to a port, the

LTC9101-2/LTC9102 ramps up the GATE pin of one or

both channels (as commanded), raising the external

MOSFET gate voltage in a controlled manner.

During a typical inrush, the MOSFET gate voltage will rise

until the external MOSFET is fully enhanced or the channel

reaches the inrush current limit (IINRUSH-2P). IINRUSH-2P is

set automatically by the PSE. When the PSE is applying

4-pair power to a single-signature PD assigned Class 0

to Class 4, IINRUSH-2P is 212.5mA (typical) per channel.

Otherwise, IINRUSH-2P is 425mA (typical) per channel.

The GATE pin will be servoed if channel current exceeds

IINRUSH-2P, actively limiting current to IINRUSH-2P. When

the GATE pin is not being servoed, the final VGS is 12V

(typical).

During inrush, each powered channel runs a timer (tSTART).

Each powered channel stays in inrush until tSTART expires.

When tSTART expires, the PSE inspects channel voltage

and current. When the PSE is applying power to a PD,

inrush is successful if the channel(s) are drawing current

below IINRUSH-2P, as appropriate per the PD configuration

and Class.

If inrush is not successful, power is removed and the

corresponding start faults are set. Otherwise, the port

or channel, as appropriate, advances to power on and

the programmed current limiting thresholds are used as

described in the Current Limit section.

Port Power Policing

The power policing threshold (4P Police) is monitored

on a per-port basis, up to 128W in 0.5W increments

(typical). When the total output power over a one second

moving average exceeds the specified threshold, power

is removed from the port and the corresponding PCUT

faults are set.

Auto Mode Maximum PSE Power

In auto mode the LTC9101-2/LTC9102 automatically

detects, classifies and powers all connected valid PDs.

In order to do this, each port must be configured for its

maximum power allocation. Select the resistor RPWRMD

from Table 11 that reflects the system’s per-port maxi-

mum power delivery capability.

Connect the PWRMD0 pin of the LTC9102 at ID address

00b to VEE through RPWRMD. The PWRMD0 pin of the

LTC9102 at ID address 01b, 10b, and 11b must be left

floating. The PWRMD1 pin of each LTC9102 must be left

floating. The PWRMD0 resistor is measured at reset.

The maximum power allocation is a reflection of the power

supply and power path capability. The PWRMD0 resistor

setting is applied to every port in this chipset, across all

quads and ICs. Accordingly, the PWRMD0 resistor must

be set with consideration for each port’s power path capa-

bility and for the system’s power supply capability.

Table 11. PWRMD0 Pin RPWRMD0 Configuration

MODE

RPWRMD

(kΩ)

PORT

MODE

0x12

DETECT/

CLASS

ENABLE

0x14

2P/4P

CONFIG

0x29

Disabled

Open

0000,0000b 0000,0000b 1000,1000b

Class 4 to 4P

14.3

1111,1111b 1111,1111b 1011,1011b

Class 5

11.0

1111,1111b 1111,1111b 1100,1100b

Class 6

8.45

1111,1111b 1111,1111b 1101,1101b

Class 7

6.49

1111,1111b 1111,1111b 1110,1110b

Class 8

1111,1111b 1111,1111b 1111,1111b

POWER CONTROL

The primary function of the LTC9101-2/LTC9102 is to con-

trol power delivery to the PSE port. With the LTC9101-2/

LTC9102, a PSE port is composed of either one or two

power channels; each power channel controls power

delivery over a pairset. Within this section, operation of

4-pair configured ports is defined per channel.

The LTC9101-2/LTC9102 delivers power by controlling

the gate drive voltage of an external power MOSFET while

monitoring the current (through an external sense resis-

tor) and the output voltage (across the OUT pin).

LTC4292 Datasheet(PDF) 26 Page - Analog Devices

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