LTC4292 datasheet(14/44 Pages) AD

14 / 44 page

LTC9101-2/LTC9102

Rev. 0

For more information www.analog.com

PIN FUNCTIONS

VSSK[12:1] (Pins 47, 46, 39, 38, 31, 30, 23, 22, 15,

14, 7, 6 Respectively): Kelvin Sense to VEE. Connect to

VEE side of sense resistor for channel n through a 0.1Ω

resistor. Do not connect directly to VEE plane. See Kelvin

Sense Requirements.

SENSE[12:1] (Pins 48, 45, 40, 37, 32, 29, 24, 21, 16, 13,

8, 5 Respectively): Current Sense Input, channel n. SENSEn

monitors the external MOSFET current via a 0.1Ω sense resis-

tor between SENSEn and VSSKn. If the voltage across the

sense resistor reaches the current limit threshold ILIM-2P, the

GATEn pin voltage is lowered to maintain constant current in

the external MOSFET. See Applications Information for further

details. If the channel is unused, tie SENSEn to VEE.

OUT[12:1] (Pins 49, 44, 41, 36, 33, 28, 25, 20, 17,

12, 9, 4 Respectively): Output Voltage Monitor, channel

n. Connect OUTn to the output channel. A current limit

foldback circuit limits the power dissipation in the external

MOSFET by reducing the current limit threshold when the

drain-to-source voltage exceeds 10V. A port power good

event is raised when the voltage from OUTn to VEE drops

below 2.4V (typ). A 500k resistor is connected internally

from OUTn to AGND when the channel is idle. If the chan-

nel is unused, the OUTn pin must float.

GATE[12:1] (Pins 50, 43, 42, 35, 34, 27, 26, 19, 18,

11, 10, 3 Respectively): Gate Drive, channel n. Connect

GATEn to the gate of the external MOSFET for channel n.

When the MOSFET is turned on, the gate voltage is driven

to 12V (typ) above VEE. During a current limit condition,

the voltage at GATEn will be reduced to maintain constant

current through the external MOSFET. If the fault timer

expires, GATEn is pulled down, turning the MOSFET off

and raising a port fault event. If the channel is unused,

the GATEn pin must float.

ID[1:0] (Pins 52, 51 respectively): Transceiver ID. Sets

the address of the LTC9102 on the multidrop high-speed

data interface. ID numbering must start at 00b. Tie high

by connecting to CAP3. Tie low by connecting to VEE. See

Device Configuration section for details.

PWRIN (Pin 55): Startup Regulator Bypass and External Low

Voltage Supply Input. Power for the internal 4.3V and 3.3V

internal supplies. An internal regulator maintains the voltage

of this pin above 6V. An external resistor or supply may be

connected to this node to improve the power efficiency of the

LTC9102. Connect a 1µF capacitor between this pin and VEE.

AGND (Pin 56): Analog Ground.

PWRMD[1:0] (Pins 57, 58 Respectively): Maximum Power

Mode Input. Connect PWRMD0 of the LTC9102 with ID[1:0]

= 00b to VEE with configuration resistor RPWRMD. When the

LTC9101-2 is reset, RPWRMD selects initial maximum power

allocation values for every port in the chipset; the system

power supply must be sized to support all ports outputting

up to RPWRMD. When auto mode is enabled, the chipset runs

independently as a PoE PSE. The chipset will detect and class

all ports and grant power to each port up to RPWRMD set-

ting. The PWRMD0 pin of LTC9102 with ID pins set to 01b,

10b, and 11b must be left floating. The PWRMD1 pin of all

LTC9102 must be left floating. See Auto Mode Maximum PSE

Power for RPWRMD options and details. The PWRMD pins are

ignored when a custom configuration package is present. See

Stored Configurations for details.

CAP4 (Pin 59): Analog Internal 4.3V Power Supply

Bypass Capacitor. Connect a 1μF ceramic cap to VEE. Do

not source or sink current from this pin.

VEE (Pins 60, 65): Main PoE Supply Input. Connect to a

–51V to –57V supply, relative to AGND. Voltage depends

on PSE Type (Type 3 or 4).

DNA (Pin 61): Data Transceiver Negative Input Output

(Analog). Connect to DND through a data transformer.

DPA (Pin 62): Data Transceiver Positive Input Output

(Analog). Connect to DPD through a data transformer.

CNA (Pin 63): Clock Transceiver Negative Input Output

(Analog). Connect to CND through a data transformer.

CPA (Pin 64): Clock Transceiver Positive Input Output

(Analog). Connect to CPD through a data transformer.

COMMON PINS

NC, DNC (LTC9101-2 Pins 4, 13; LTC9102 Pins 53,

54): All pins identified with “NC” or “DNC” must be left

unconnected.

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