Data Sheet

LT3041

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. 0 | 7 of 36

Figure 3. Pin Configuration

Table 3. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 2, 3

IN

Input. The IN pins supply power to the regulator. The LT3041 requires a bypass capacitor at the IN pin. In general, the output impedance of

a battery rises with frequency; therefore, it is best practice to include a bypass capacitor in battery-powered applications. While a 10 µF input

bypass capacitor generally suffices, applications with large load transients can require higher input capacitance to prevent input-supply droop.

Refer to the Stability and Input Capacitance and PSRR and Input Capacitance sections on the proper use of an input capacitor and its effect

on circuit performance, in particular PSRR. The LT3041 withstands reverse voltages on IN with respect to GND, OUTS, and OUT. In the case

of a reversed input, which occurs if a battery is plugged in backwards, the LT3041 acts as if a diode is in series with its input. Therefore, no

reverse-current flows into the LT3041, and no negative voltage appears at the load. The device protects itself and the load.

4

VIOC

Voltage for Input-to-Output Control. The LT3041 incorporates a tracking function to control the switching preregulator powering the LT3041. The

VIOC pin is the output of this tracking function that drives the feedback (FB) pin of the preregulator to maintain the input voltage of the LT3041

at VOUT + VVIOC. This function minimizes power dissipation while maintaining PSRR performance. Refer to the High-Efficiency Linear Regulator:

Voltage Input-to-Output Control (VIOC) section for further details.

5

EN/UV

Enable and UVLO. Pulling the EN/UV pin low moves the LT3041 to shutdown mode. Quiescent current in shutdown mode drops to 18 µA and

the output voltage turns off. Alternatively, the EN/UV pin can set an input-supply UVLO threshold by using a resistor-divider between IN, EN/UV,

and GND. The LT3041 typically turns on when the EN/UV voltage exceeds 1.28 V on its rising edge, with a 110 mV hysteresis on its falling

edge. The EN/UV pin can be driven above the input voltage and maintain proper functionality. If unused, connect EN/UV to IN. Do not float the

EN/UV pin.

6

PG

Power Good. PG is an open-drain flag that indicates output-voltage regulation. PG pulls low if PGFB is less than 302 mV. If the power-good

functionality is not needed, float the PG pin. A parasitic substrate diode exists between the PG and GND pins of the LT3041; therefore, do not

drive PG more than 0.3 V less than GND during normal operation or during a fault condition.

7

ILIM

Current-Limit Programming Pin. Connecting a resistor between ILIM and GND programs the current limit. For best accuracy, Kelvin connect

this resistor directly to the GND pin of the LT3041. The programming-scale factor is nominally 150 mA × kΩ. The ILIM pin sources current

proportional (1:500) to the output current. Therefore, ILIM also serves as a current-monitoring pin with a 0 V to 300 mV range. If the

programmable current-limit functionality is not needed, connect ILIM to GND. A parasitic substrate diode exists between the ILIM and GND pins

of the LT3041; therefore, do not drive ILIM more than 0.3 V less than GND during normal operation or during a fault condition.

8

PGFB

Power-Good Feedback. The PG pin pulls high if PGFB increases beyond 302 mV on its rising edge, with 7 mV hysteresis on its falling edge.

Connecting an external resistor-divider between OUT, PGFB, and GND sets the programmable power-good threshold with the following transfer

function: 0.302 V × (1 + RPG2/RPG1). As discussed further in the Fast Startup section, PGFB also activates the fast start-up circuitry. Connect

PGFB to IN if the power-good and fast start-up functions are not needed. In addition, if reverse-input protection is additionally required, connect

the anode of a 1N4148 diode to IN and its cathode to PGFB. Refer to Figure 96 for further details. A parasitic-substrate diode exists between

the PGFB and GND pins of the LT3041; therefore, do not drive PGFB more than 0.3 V less than GND during normal operation or during a fault

condition.

9

SET

The Inverting Input of the Error Amplifier and the Regulation Set Point for the LT3041. SET sources precision 100 µA current that flows through

an external resistor connected between SET and GND. The output voltage of the LT3041 is determined by VSET = ISET × SET resistance (RSET).

The output voltage range is from 0.2 V to 15 V. Adding a capacitor from SET to GND improves noise, PSRR, and transient response at the

expense of an increased start-up time. For optimum load regulation, Kelvin connect the ground side of the SET pin resistor directly to the load.

A parasitic-substrate diode exists between the SET and GND pins of the LT3041; therefore, do not drive SET more than 0.3 V less than GND

during normal operation or during a fault condition.

10, 11

GND

Ground.

12

OUTS

Output Sense. The OUTS pin is the noninverting input to the error amplifier. For optimal transient performance and load regulation, Kelvin

connect OUTS directly to the output capacitor and the load. In addition, connect the GND connections of the output capacitor and the SET pin

capacitor directly together. A parasitic-substrate diode exists between the OUTS and GND pins of the LT3041; therefore, do not drive OUTS

more than 0.3 V less than GND during normal operation or during a fault condition.