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LT3041 Datasheet(PDF) 29 Page - Analog Devices

Part # LT3041
Description  20 V, 1 A, Ultra-Low Noise, Ultra-High PSRR Linear Regulator with VIOC Control
PDF  36 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

LT3041 Datasheet(HTML) 29 Page - Analog Devices

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Data Sheet
LT3041
APPLICATIONS INFORMATION
analog.com
Rev. 0 | 29 of 36
Figure 86. Input and Output Noise Spectral Density of the LT3041
THERMAL CONSIDERATIONS
The LT3041 has internal power and thermal limiting circuits that
protect the device under overload conditions. The thermal shut-
down temperature is nominally 169°C with about 5°C of hysteresis.
For continuous normal load conditions, do not exceed the maximum
junction temperature, 125°C. It is important to consider all sources
of thermal resistance from junction to ambient, which includes
junction to case, case to heatsink interface, heatsink resistance,
or circuit board to ambient as the application dictates. Additionally,
consider all heat sources close to the LT3041.
The underside of the DFN package has exposed metal from the
lead frame to the die attachment. This package allows heat to
directly transfer from the die junction to the PCB metal to limit
maximum operating junction temperature. The dual, inline pin ar-
rangement allows metal to extend beyond the ends of the package
on the topside (component side) of the PCB.
For surface-mount devices, heat sinking is accomplished by using
the heat spreading capabilities of the PCB and its copper traces.
Copper board stiffeners and plated throughholes can also be used
to spread the heat generated by the LDO regulator.
Table 6 lists the thermal resistance as a function of the copper
area on a fixed board size. All measurements were taken in still
air on a 4 layer FR4 board with 1 oz solid internal planes and
2 oz top and bottom planes with a total board thickness of 1.6
mm. The four layers were electrically isolated with no thermal vias
present. PCB layers, copper weight, board layout, and thermal
vias affect the resultant thermal resistance. For more information
on thermal resistance and high thermal conductivity test boards,
refer to JEDEC standard JESD-51, JESD51-7, and JESD51-12.
Achieving low thermal resistance necessitates careful PCB layout.
Table 6. Measured Thermal Resistance for DFN Package
Copper Area
Board Area
Thermal
Resistance
Top Side1
Bottom Side
2500 mm2
2500 mm2
2500 mm2
34°C/W
1000 mm2
2500 mm2
2500 mm2
34°C/W
225 mm2
2500 mm2
2500 mm2
36°C/W
100 mm2
2500 mm2
2500 mm2
37°C/W
1 The device is mounted on the topside.
CALCULATING JUNCTION TEMPERATURE
For example, given an output voltage of 3.3 V, an input voltage
of 5 V ± 5%, an output current range from 1 mA to 1 A, and
a maximum ambient temperature of 50°C, what is the maximum
junction temperature?
The power dissipation of the LT3041 is the following:
IOUTMAX× VINMAX−VOUT +IGND
×VINMAX
(7)
where:
IOUT(MAX) = 1 A.
VIN(MAX) = 5.25 V.
IGND (at IOUT = 1 A and VIN = 5.25 V) = 27 mA.
Therefore, PDISS = 1 A × (5.25 V − 3.3 V) + 27 mA × 5.25 V = 2.1
W.
Using a DFN package, the thermal resistance is in the range of
34°C/W to 37°C/W depending on the copper area. Therefore, the
junction temperature rise above ambient approximately equals 2.1
W × 35°C/W = 73.5°C.
The maximum junction temperature equals the maximum ambient
temperature plus the maximum junction temperature rise above
ambient, which calculates as follows:
TJMAX=50°C+73.5°C=123.5°C
(8)
OVERLOAD RECOVERY
Like many IC power regulators, the LT3041 incorporates SOA pro-
tection. The SOA protection activates at input-to-output differential
voltages greater than 11 V. The SOA protection decreases the
current limit because the input-to-output differential increases and
keeps the power transistor inside a safe operating region for all
values of input-to-output voltages up to the Absolute Maximum
Ratings of the LT3041. The LT3041 provides some level of output
current for all values of input-to-output differentials. Refer to the
Figure 32. When power is first applied and input voltage rises, the
output follows the input and keeps the input-to-output differential
low to allow the LDO regulator to supply the large output current
and startup into high-current loads.
Due to current-limit foldback, however, at high-input voltages, a
problem can occur if the output voltage is low, and the load current
is high. Such situations occur after the removal of a short-circuit



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