MPC8540 datasheet(315/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

7-11

The L2CEWCRn registers contain identical fields, which are described in Table 7-4.

7.3.1.4

L2 Memory-Mapped SRAM Base Address Registers 0–1

(L2SRBARn)

The L2 memory-mapped SRAM base address registers (L2SRBARn), shown in Figure 7-10,

control the memory-mapped SRAM mode functionality. Specified addresses must be aligned to

the value in L2CTL[L2BLKSZ]. If L2CTL[L2SRAM] specifies one memory-mapped SRAM

block, its base address must be written to L2SRBAR0; if it specifies two memory-mapped SRAM

blocks, L2SRBAR0 and L2SRBAR1 are used.

Table 7-4. L2CEWCRn Field Descriptions

Bits

Name

Description

External write enable. An external write matching the address window defined by

L2CEWARn/L2CEWCRn is allocated or updated in the L2 cache.

0 External writes for the L2CEWARn/L2CEWCRn pair are disabled.

1 External writes are enabled for the L2CEWARn/L2CEWCRn pair.

LOCK

Lock lines in the targeted cache. An external write matching the address window defined by

L2CEWARn/L2CEWCRn is locked in the L2 cache when it is allocated or updated.

0 The locked bit is not set when a line is allocated unless explicitly specified by transaction attributes.

1 Cache lines are allocated as locked. A hit to a valid, unlocked lines sets the lock.

2–7

—

Reserved

8–31 SIZMASK Mask size. Defines the size of the naturally aligned address region for cache external writes. The

address region must be aligned to a boundary that is a multiple of the mask size. Any value not listed

below is illegal and produces boundedly undefined results.

1111 1111 1111 1111 1111 1111 256 bytes

1111 1111 1111 1111 1111 1110 512 bytes

1111 1111 1111 1111 1111 1100 1 Kbyte

1111 1111 1111 1111 1111 1000 2 Kbytes

1111 1111 1111 1111 1111 0000 4 Kbytes

1111 1111 1111 1111 1110 0000 8 Kbytes

1111 1111 1111 1111 1100 0000 16 Kbytes

1111 1111 1111 1111 1000 0000 32 Kbytes

1111 1111 1111 1111 0000 0000 64 Kbytes

1111 1111 1111 1110 0000 0000 128 Kbytes

1111 1111 1111 1100 0000 0000 256 Kbytes

1111 1111 1111 1000 0000 0000 512 Kbytes

1111 1111 1111 0000 0000 0000 1 Mbyte

1111 1111 1110 0000 0000 0000 2 Mbytes

1111 1111 1100 0000 0000 0000 4 Mbytes

1111 1111 1000 0000 0000 0000 8 Mbytes

1111 1111 0000 0000 0000 0000 16 Mbytes

1111 1110 0000 0000 0000 0000 32 Mbytes

1111 1100 0000 0000 0000 0000 64 Mbytes

1111 1000 0000 0000 0000 0000 128 Mbytes

1111 0000 0000 0000 0000 0000 256 Mbytes

1110 0000 0000 0000 0000 0000 512 Mbytes

1100 0000 0000 0000 0000 0000 1 Gbyte

1000 0000 0000 0000 0000 0000 2 Gbytes

0000 0000 0000 0000 0000 0000 4 Gbytes

17 18

ADDR

0000

Reset

All zeros

Offset

0x2_0100, 0x2_0108

Figure 7-10. L2 Memory-Mapped SRAM Base Address Registers (L2SRBARn)

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