MPC8540 datasheet(319/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

7-15

7.3.1.5.2

Error Control and Capture Registers

The error control and capture registers control detection and reporting of tag parity, ECC and L2

configuration errors. L2 configuration errors are illegal combinations of L2 size and block size and

are detected when the L2 is enabled (L2CTL[L2E] = 1). Figure 7-14 shows the L2 error capture

data high register (L2CAPTDATAHI).

Table 7-9 describes L2CAPTDATAHI[L2DATA] fields.

Figure 7-15 shows the L2 error capture data low register (L2CAPTDATALO).

DERRIEN

L2 data array error injection enable

0 No data errors are injected.

1 Subsequent entries written to the L2 data array have data or ECC bits inverted as specified

in the data and ECC error injection masks and/or data path byte mirrored onto ECC as

specified by ECC mirror byte enable.

Note: if both ECC mirror byte and data error injection are enabled, ECC mask error injection is

performed on the mirrored ECC.

24–31

ECCERRI

Error injection mask for the ECC bits. A set bit corresponding to an ECC bit causes that bit to be

inverted on SRAM writes if DERRIEN = 1.

RL2DATA

Reset

All zeros

Offset

0x2_0E20

Figure 7-14. L2 Error Capture Data High Register (L2CAPTDATAHI)

Table 7-9. L2CAPTDATAHI Field Description

Bits

Name

Description

0–31

L2DATA

L2 data high word

RL2DATA

Reset

All zeros

Offset

0x2_0E24

Figure 7-15. L2 Error Capture Data Low Register (L2CAPTDATALO)

Table 7-8. L2ERRINJCTL Field Descriptions (continued)

Bits

Name

Description

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