MPC8540 datasheet(320/1302 Pages) FREESCALE

320 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

7-16

Freescale Semiconductor

L2 Look-Aside Cache/SRAM

Table 7-10 describes L2CAPTDATALO[L2DATA] fields.

Figure 7-16 shows the L2 error syndrome register (L2CAPTECC).

Table 7-11 describes L2CAPTECC fields.

Figure 7-17 shows the L2 error detect register (L2ERRDET).

Table 7-12 describes L2ERRDET fields.

Table 7-10. L2CAPTDATALO Field Description

Bits

Name

Description

0–31

L2DATA

L2 data low word

23 24

ECCSYND

0000

ECCCHKSUM

Reset

All zeros

Offset

0x2_0E28

Figure 7-16. L2 Error Syndrome Register (L2CAPTECC)

Table 7-11. L2CAPTECC Field Descriptions

Bits

Name

Description

0–7

ECCSYND

The calculated ECC syndrome of the failing double word

8–23

—

Reserved

24–3

ECCCHKSU

The data path ECC of the failing double word

R MULL2ERR 0000 0000 00000 0000 00000 000 0

TPARERR MBECCERR SBECCERR

L2CFGDIS

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x2_0E40

Figure 7-17. L2 Error Detect Register (L2ERRDET)

Table 7-12. L2ERRDET Field Descriptions

Bits

Name

Description

MULL2ERR

Multiple L2 errors (bit reset, write 1 to clear)

0 Multiple L2 errors of the same type were not detected.

1 Multiple L2 errors of the same type were detected.

1–26

—

Reserved

MPC8540 Datasheet(PDF) 320 Page - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 320 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL