MPC8540 datasheet(322/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

7-18

Freescale Semiconductor

L2 Look-Aside Cache/SRAM

Figure 7-19 shows the L2 error interrupt enable register (L2ERRINTEN). When an enabled error

condition exists, the L2 signals an interrupt to the core through the internal int signal.

Table 7-14 describes L2ERRINTEN fields.

SBECCDIS Single-bit ECC error disable

0 Single-bit ECC error detection enabled

1 Single-bit ECC error detection disabled

—

Reserved

L2CFGDIS

L2 configuration error disable

0 L2 configuration error detection enabled

1 L2 configuration error detection disabled

026

R 0 0 000 000 000 000 000 000 000 000 0

TPARINTEN MBECCINTEN SBECCINTEN

L2CFGINTEN

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x2_0E48

Figure 7-19. L2 Error Interrupt Enable Register (L2ERRINTEN)

Table 7-14. L2ERRINTEN Field Descriptions

Bits

Name

Description

0–26

—

Reserved

TPARINTEN

Tag parity error reporting enable

0 Tag parity error reporting disabled

1 Tag parity error reporting enabled

MBECCINTEN

Multiple-bit ECC error reporting enable. Note that uncorrectable read errors may

cause the assertion of core_fault_in, which causes the core to generate a machine

check interrupt, unless it is disabled (by clearing HID1[RFXE]). If RFXE is zero and this

error occurs, L2ERRDIS[MBECCDIS] must be cleared and MBECCINTEN must be

set to ensure that an interrupt is generated. For more information, see Section 6.10.2,

“Hardware Implementation-Dependent Register 1 (HID1).”

0 Multiple-bit ECC error reporting disabled

1 Multiple-bit ECC error reporting enabled

SBECCINTEN

Single-bit ECC error reporting enable

0 Single-bit ECC error reporting disabled

1 Single-bit ECC error reporting enabled

—

Reserved

L2CFGINTEN

L2 configuration error reporting enable

0 L2 configuration error reporting disabled

1 L2 configuration error reporting enabled

Table 7-13. L2ERRDIS Field Descriptions (continued)

Bits

Name

Description

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