MPC8540 datasheet(321/1302 Pages) FREESCALE

321 / 1302 page

Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

7-17

Figure 7-18 shows the L2 error disable register (L2ERRDIS).

Table 7-13 describes L2ERRDIS fields.

TPARERR

Tag parity error (bit reset, write 1 to clear)

0 Tag parity error was not detected

1 Tag parity error was detected

Note that if an L2 cache tag parity error occurs on an attempt to write a new line, the L2 cache must

be flash invalidated. L2 functionality is not guaranteed if flash invalidation is not performed after a tag

parity error.

MBECCERR Multiple-bit ECC error (bit reset, write 1 to clear)

0 Multiple-bit ECC errors were not detected.

1 Multiple-bit ECC errors were detected.

SBECCERR Single-bit ECC error (bit reset, write 1 to clear)

0 Single-bit ECC error was not detected

1 Single-bit ECC error was detected

—

Reserved

L2CFGERR

L2 configuration error (bit reset, write 1 to clear). Reports inconsistencies between the L2SIZ,

L2BLKSZ, and L2SRAM settings of the L2 control register (L2CTL).

0 L2 configuration errors were not detected

1 L2 illegal configuration error detected

026

R 000 0000 0000 0000 00000 0000 00 0

TPARDIS

MBECCDIS SBECCDIS

L2CFGDIS

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x2_0E44

Figure 7-18. L2 Error Disable Register (L2ERRDIS)

Table 7-13. L2ERRDIS Field Descriptions

Bits

Name

Description

0–26

—

Reserved

TPARDIS

Tag parity error disable

0 Tag parity error detection enabled

1 Tag parity error detection disabled

MBECCDIS Multiple-bit ECC error disable. Note that uncorrectable read errors may cause the assertion of

core_fault_in, which causes the core to generate a machine check interrupt, unless it is disabled (by

clearing HID1[RFXE]). If RFXE is zero and this error occurs, MBECCDIS must be cleared and

L2ERRINTEN[MBECCINTEN] must be set to ensure that an interrupt is generated. For more

information, see Section 6.10.2, “Hardware Implementation-Dependent Register 1 (HID1).”

0 Multiple-bit ECC error detection enabled

1 Multiple-bit ECC error detection disabled

Table 7-12. L2ERRDET Field Descriptions (continued)

Bits

Name

Description

MPC8540 Datasheet(PDF) 321 Page - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 321 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL