MPC8540 datasheet(324/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

7-20

Freescale Semiconductor

L2 Look-Aside Cache/SRAM

Figure 7-21 shows the L2 error address capture register (L2ERRADDR).

Table 7-16 describes L2ERRADDR[L2ADDR] fields.

Figure 7-22 shows the L2 error control register (L2ERRCTL).

Table 7-17 describes L2ERRCTL fields.

L2ADDR

Reset

All zeros

Offset

0x2_0E50

Figure 7-21. L2 Error Address Capture Register (L2ERRADDR)

Table 7-16. L2ERRADDR Field Description

Bits

Name

Description

0–31

L2ADDR

L2 address corresponding to detected error

1516

2324

R 0000

0000

L2CTHRESH

0000

L2CCOUNT

Reset

All zeros

Offset

0x2_0E58

Figure 7-22. L2 Error Control Register (L2ERRCTL)

Table 7-17. L2ERRCTL Field Descriptions

Bits

Name

Description

0–7

—

Reserved

8–15

L2CTHRESH L2 cache threshold. Threshold value for the number of ECC single-bit errors that are detected

before reporting an error condition

16–23

—

Reserved

24–31

L2CCOUNT

L2 count. Counts ECC single-bit errors detected. If L2CCOUNT equals the ECC single-bit error

trigger threshold, an error is reported if single-bit error reporting is enabled

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