MPC8540 datasheet(325/1302 Pages) FREESCALE

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External Writes to the L2 Cache (Cache Stashing)

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

7-21

7.4

External Writes to the L2 Cache (Cache Stashing)

Data from an I/O master can be allocated into the L2 cache while simultaneously being written to

memory. External writes can be performed from any I/O master:

•

Ethernet

•RapidIO

•PCI

•DMA

New cache lines are allocated for full cache line writes, unless the line is already valid or locked.

Sub–cache-line write data is stashed only if the line is valid in the cache. A read-modify-write

process is used to merge the stashed data with the valid line data.

The L2 cache external write address registers 0–3 (L2CEWARn) are paired with the L2 cache

external write control registers 0–3 (L2CEWCRn) to control the cache stashing functionality. Each

that can be locked with a snoop write transaction. The address register must be naturally aligned

to the window size in the corresponding control register. For more information, see

Section 7.3.1.2, “L2 Cache External Write Address Registers 0–3 (L2CEWARn),” and

Section 7.3.1.3, “L2 Cache External Write Control Registers 0–3 (L2CEWCRn).”

Note that stashing can occur regardless of whether the L1 cache is enabled.

Note that stashing can also occur even if the cache-inhibited bit in the MMU is set for the page.

When the core looks for (and does not find) the stashed data in the L1 cache, a transaction is

generated in which the L2 cache responds by updating the L1 cache with the requested data.

For information on how to initiate cache stashing, see the respective chapters for the I/O masters,

listed above, that support stashing.

7.5

L2 Cache Timing

Table 7-18 shows the timing of back-to-back loads that miss in the L1 data cache and hit in the L2

cache, assuming the core is running at 2 1/2 times the L2 cache frequency. The L2 returns the 128

bits containing the requested data (critical quad word) first. This data is forwarded to the result

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