MPC8540 datasheet(329/1302 Pages) FREESCALE

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L2 Cache Locking

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

7-25

— Flash clearing of all instruction and/or data locks can be done by writes to configuration

registers.

— An unlock attribute can be attached to I/O read operations.

7.7.1

Locking the Entire L2 Cache

The entire L2 cache can be locked by setting L2CTL[L2DO] = 1 and L2CTL[L2IO] = 1. This has

the effect of preventing any further allocation of new lines in the cache by core requests. If there

are lines in the cache that are not valid, they cannot be used by core requests until the cache is

unlocked. While the cache is locked, read requests are serviced as normal, and snooping continues

as normal to maintain coherency. Lines invalidated to satisfy coherency requirements cannot be

reallocated by core requests while the cache remains locked. The L2 cache can be unlocked by

clearing L2CTL[L2IO] and/or L2CTL[L2DO]. Note that L2CTL[L2DO] and L2CTL[L2IO] have

no effect on cache external write allocations or memory-mapped SRAM.

Note that this form of cache locking does not use the lock bits of the cache and cannot be cleared

by resetting the cache or lock bits.

7.7.2

Locking Programmed Memory Ranges

A programmed memory range can be locked with a snoop write transaction that matches a cache

external write address range (specified by L2CEWARn and L2CEWCRn). There is no clearing of

locks through the programmed address ranges. Locks can be cleared using clear lock instructions,

flushes, or read-and-clear-lock snoop (RWNITC with clear lock attribute), or flash clear locks.

7.7.3

Locking Selected Lines

Individual lines are locked when the L2 receives one of the following burst transactions:

•

icbtls (CT = 1)—Instruction Cache Block Touch and Lock Set instruction

•

dcbtls (CT = 1)—Data Cache Block Touch and Lock Set instruction

•

dcbtstls (CT = 1)—Data Cache Block Touch for Store and Lock Set instruction

•

Snoop burst write—If the address hits on a programmed cache external write space with the

lock attribute set, or if the write allocate transaction type is used

•

Snoop non-burst write—If the address hits on a programmed cache external write space

with the lock attribute set

Note that the core complex broadcasts these instructions to the L2 if the CT field in the instruction

specifies the L2 cache (CT = 1). When the L2 cache is specified, data is not placed in the L1, only

the L2. If the L1 cache is specified (CT = 0), the L2 does not lock the line, and the data is placed

in the L1 (and locked).

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