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MPC8540 Datasheet(PDF) 332 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 332 Page - Freescale Semiconductor, Inc |
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332 / 1302 page  MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 7-28 Freescale Semiconductor L2 Look-Aside Cache/SRAM Figure 7-23. L2 Cache Line Replacement Algorithm 7.8.1 PLRU Bit Update Considerations PLRU bits are updated when a way is modified, either by a write, an invalidate, or an allocation of a new line. PLRU bit updates depend on which cache way was last accessed, as summarized in Table 7-19. When an L2 line is invalidated, the PLRU bits are updated, marking the corresponding way as least-recently-used. This causes the invalidated way to be selected as the next victim. Table 7-19. PLRU Bit Update Algorithm Last Way Accessed PLRU Bits P 0 P 1 P 2 P 3 P 4 P 5 P 6 0 1 1— 1— — — 1 1 1— 0— — — 21 0 — — 1 — — 31 0 — — 0 — — 40 — 1 — — 1 — 50 — 1 — — 0 — 6 0 —0 — — —1 7 0 —0 — — —0 P0 = 0? P1 = 0? P2 = 0? P3 = 0? P5 = 0? P4 = 0? P6 = 0? Allocate W0 Allocate W1 Allocate W2 Allocate W3 Allocate W4 Allocate W5 Allocate W6 Allocate W7 Yes Yes Yes Yes Yes Yes No No No No No No Yes No P0 P1 P2 P3 P4 P6 0 0 x 0 P5 x x x 0 1 x x 0 x x 0 1 x x 1 x x 0 0 x 1 x x x 1 x 0 x x 0 x 1 x 0 x x 1 x 1 x 1 x x x 0 1 x 1 x x x 1 |
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