MPC8540 datasheet(334/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

7-30

Freescale Semiconductor

L2 Look-Aside Cache/SRAM

Table 7-21 shows L2 cache states. Note that these conventions are also used in Table 7-22.

7.9.2

Flash Invalidation of the L2 Cache

The L2 cache may be completely invalidated by setting the L2I bit of the L2 control register

(L2CTL). Note that no data is lost in this process because the L2 cache is a write-through cache

and contains no modified data. Flash invalidation of the cache is necessary when the cache is

initially enabled and may be necessary to recover from some error conditions such as a tag parity

error.

The invalidation process requires several cycles to complete. The L2I bit remains set during this

procedure and is then cleared automatically when the procedure is complete. The L2 cache

controller issues retries for all transactions on the e500 core complex bus (CCB) while the flash

invalidation process is in progress.

Note that the contents of memory-mapped SRAM regions of the data array are unaffected by a

flash invalidation of the L2 cache regions fo the array.

7.9.3

L2 State Transitions

Table 7-22 lists state transitions for all e500 core-initiated transactions that change the L2 cache

state. Core-initiated transactions caused when the core executes msync, mbar, tlbivax, or tlbsync

do not change the L2 cache state. The table does not list initial L1 states for transactions that hit

in the L1 (iL1 or dL1) and are not sent to the L2.

In the table, the heading ‘L2 hit’ indicates that the L2 provides (on a read) or captures (on a write)

data for an existing line. Some entries list two final L1 states. L2 touch instructions never allocate

into iL1 or dL1.

Table 7-21. L2 Cache States

L2 states

xxx

Invalid (I)

1000

Exclusive (E)

1001

Exclusive data locked (EDL)

1010

Exclusive instruction locked (EIL)

1011

Exclusive instruction and data locked (EL)

1100

Stale (data invalid, locks invalid) (T)

1101

Stale (data invalid, dlock valid) (TDL)

1110

Stale (data invalid, ilock valid) (TIL)

1111

Stale (data invalid, locks valid) (TL)

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