MPC8540 datasheet(337/1302 Pages) FREESCALE

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L2 Cache Operation

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

7-33

Table 7-23 lists L2 cache state transitions for all system-initiated (non-core) transactions that

change the L2. The transaction types and attributes listed follow MPX bus nomenclature, with the

addition of write allocate (burst write with L2 cache allocation). Table 7-23 accounts for changes

caused by L1 snoop pushes triggered by snoops, listed in Table 7-22.

dcbtls_L2

icbtls_L2

dcbtstls_L2

dL1

An icbtls_L2 that hits modified in L1 cannot be

distinguished from dcbtls_L2 and sets the L2 dlock

bit. If software shares cache lines between

instructions and data and wishes to set ilocks in L2,

it must perform dcbst to flush the line out of the dL1

before locking it in L2.

E/EL/T

Yes

Snoop push

dL1

I/E

EL/T

I/E

Invalidate data, keep lock

dcbf

dcbst

dL1

I/E/EL

dcbz

dcba

dL1

I/E

dcbi

dL1

I,E,M

E/EL/T

dcbf

dcbst

dL1

I,E

E/EL/T

icbi

iL1

I,V

E/EL/T

Table 7-23. State Transitions Due to System-Initiated Transactions

Transaction Type

ci gbl

Initial L2

State

Final L2 State

Comments

Clean

IKill

I/E/EL/T

Same

Flush

I/E/EL/T

Write allocate

I/E/EL/T

Allocate and lock regardless of cache external

write (CEW) window

I/E

Allocate regardless of CEW window

EL/T

I/E

No allocate if cache-inhibited

EL/T

Invalidate data, keep lock

Table 7-22. State Transitions Due to Core-Initiated Transactions (continued)

Source of Transaction

Initial States

Hit

Final States

Comments

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