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MPC8540 Datasheet(PDF) 336 Page - Freescale Semiconductor, Inc

Part # MPC8540
Description  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 336 Page - Freescale Semiconductor, Inc

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
7-32
Freescale Semiconductor
L2 Look-Aside Cache/SRAM
Cacheable load (3-state)
Cacheable lwarx (3-state)
dcbt_L1 (3-state)
dcbtls_L1 (3-state)
dL1
I
I
No
E/I
I
L2CTL[L2IO] = 1
T
No
E/I
T
L2CTL[L2IO] = 1
E
Yes
E/I
I
L2CTL[L2IO] = 1
EL
Yes
E/I
T
L2CTL[L2IO] = 1
I
No
E/I
E
L2CTL[L2IO] = 0
dcbt_L2
dcbtst_L2
dL1
I,E
E/EL
Yes
E/I
Same
L2CTL[L2IO] = 0
T
No
E/I
EL
L2CTL[L2IO] = 0. Restore locked line with valid
data from bus
dcbtst_L1
dcbtstls_L1
dL1
I
I/T
No
E
Same
EYes
E
I
EL
Yes
E
T
dcbtls_L2
dcbtstls_L2
dL1
I,E
I
No
I
I
L2CTL[L2IO] = 1
T
No
I
T
L2CTL[L2IO] = 1
E
Yes
I
I
L2CTL[L2IO] = 1
EL
Yes
I
T
L2CTL[L2IO] = 1
I
No
I
EL
L2CTL[L2IO] = 0
E/EL
Yes
I
EL
L2CTL[L2IO] = 0
T
No
I
EL
L2CTL[L2IO] = 0. Restore locked line with valid
data from bus
Write-through store
dL1
I,E,M
I/T
No
Same
I
E/EL
Yes
Same
Same
Read-modify-write
Cache-inhibited store
N/A
I/E
No
N/A
I
Invalidate line
EL/T
No
N/A
T
Invalidate data, keep lock
Cache-inhibited stwcx.
N/A
I/E
No
N/A
I
Invalidate line
EL/T
No
N/A
T
Invalidate data, keep lock
dcblc_L2
icblc_L2
dL1
I,E,M
I/E
No
Same
Same
EL
No
Same
E
TNo
Same
I
Victim castout
dcbt_L2
icbt_L2
dcbtst_L2
dL1
M
I/T
No
I
Same
L2CTL[L2IO] = 1. If software sharing cache lines
between instructions and data wishes to capture
instruction lines in L2 with L2CTL[L2IO] = 1, it must
perform dcbst to flush the line out of the dL1 before
fetching it into L2.
I
No
I
E
L2CTL[L2IO] = 0
E/EL
No
I
I/T
L2CTL[L2IO] = 1
Yes
I
Same
L2CTL[L2IO] = 0
T
Yes
I
EL
L2CTL[L2IO = 0
Table 7-22. State Transitions Due to Core-Initiated Transactions (continued)
Source of Transaction
Initial States
L2
Hit
Final States
Comments
L1
L2
L1
L2



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