MPC8540 datasheet(333/1302 Pages) FREESCALE

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L2 Cache Operation

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

7-29

7.8.2

Allocation of Lines

L2 cache lines are locked through the status array lock bits. There are two lock bits for each way

of each set (1024 sets by eight ways). These bits are set or cleared through special L2 controller

commands.

Lock bits are used at allocate time to steer the PLRU algorithm away from selecting locked

victims. In the following discussion, the eight lock bits for a particular set are called L0–L7.

Where Lock Way i: Li = Di | Ii, i=0...7 (Di = data lock, Ii = instruction lock)

An effective value of each PLRU bit is calculated as follows:

P0_eff = f(P0,L0,L1,L2,L3,L4,L5,L6,L7) = (L0 & L1 & L2 & L3) | (P0 & ~(L4 & L5 & L6 & L7))

P1_eff = f(P1,L0,L1,L2,L3) = (L0 & L1) | (P1 & ~(L2 & L3))

P2_eff = f(P2,L4,L5,L6,L7) = (L4 & L5) | (P2 & ~(L6 & L7))

P3_eff = f(P3,L0,L1) = L0 | (P3 & ~L1)

P4_eff = f(P4,L2,L3) = L2 | (P4 & ~L3)

P5_eff = f(P5,L4,L5) = L4 | (P5 & ~L5)

P6_eff = f(P6,L6,L7) = L6 | (P6 & ~L7)

These effective PLRU bits are used to select a victim, as indicated in Table 7-20.

7.9

L2 Cache Operation

This section describes the behavior of the L1 and L2 cache in response to various operations and

in various configurations.

7.9.1

L2 Cache States

The L2 status array uses four bits for each line to determine the status of the line. Different

combinations of these bits result in different L2 states. The status bits are as follows:

•

Valid (V)

•

Instruction locked (IL)

•

Data locked (DL)

•

Stale (T)

Table 7-20. PLRU-Based Victim Selection Mechanism

Way Selected

PLRU State (Binary)

Reduced Logic

Equation

00x0xxx

~P0 & ~P1 & ~P3

00x1xxx

~P0 & ~P1 & P3

01xx0xx

~P0 & P1 & ~P4

01xx1xx

~P0 & P1 & P4

1x0xx0x

P0 & ~P2 & ~P5

1x0xx1x

P0 & ~P2 & P5

1x1xxx0

P0 & P2 & ~P6

1x1xxx1

P0 & P2 & P6

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