MPC8540 datasheet(330/1302 Pages) FREESCALE

330 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

7-26

Freescale Semiconductor

L2 Look-Aside Cache/SRAM

When the touch lock set L2 instruction (dcbtls or dcbtstls) hits are modified in the L1 cache, the

modified data is allocated into the L2 cache (and written back to main memory) and a data lock is

set. The L1 line state transitions to invalid.

Note that if the L2 receives a request to allocate and lock a line, but all lines in the selected way

are locked, the requested L2 line is not allocated and the L2 cache lock overflow bit

(L2CTL[L2LO]) is set.

Lines invalidated to satisfy coherency requirements cannot be reallocated while the cache remains

locked.

7.7.4

Clearing Locks on Selected Lines

Individual locks in the L2 are cleared by a lock clear (icblc or dcblc, CT = 1) instruction. This

directs the L2 cache to clear a lock on that line if it hits in the L2 cache. Both data and instruction

locks are cleared by the icblc and dcblc instructions.

Note that the lock on a line is cleared if the line is invalidated by a snooped flush transaction, and

the line in the cache is available for allocation of a new line of instruction or data unless the entire

cache is locked.

NOTE

There is a scenario in which a lock clear operation appears to fail to

clear a lock in the L2 cache. This occurs only when the attempt to set

the lock results in a bus error (for example, PCI returns an error

condition).

Assume the following scenario:

1. The e500 attempts to set a lock in the L2 cache (by executing a

dcbtls or icbtls instruction with CT = 1). The line is not already

present in the cache, so it must be read from external memory. This

read encounters an error which, depending on the chip configuration,

will be reported to the core (probably as an interrupt).

2. At (or near) the same time, a cache external write to the same cache

line is being mastered by the ECM.

3. Very soon after the cache external write, a transaction to clear the

lock occurs. This can be caused by the processor executing a dcblc or

icblc instruction with CT = 1, or by the ECM mastering a lock clear

transaction.

If this scenario occurs within a tight timing window, the cache line

may unexpectedly remain locked at the end of the sequence.

MPC8540 Datasheet(PDF) 330 Page - Freescale Semiconductor, Inc