MPC8540 datasheet(331/1302 Pages) FREESCALE

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PLRU L2 Replacement Policy

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

7-27

The interrupt handler may want to clear the erroneously remaining

lock in this case.

7.7.5

Flash Clearing of Instruction and Data Locks

Locks for instructions and data are recorded separately in the L2 cache, and they can be flash

cleared separately by writing the appropriate value to the L2 cache control register

(L2CTL[L2LFR] and L2CTL[L2LFRID]). Flash invalidating of the L2 (setting L2CTL[L2I])

clears all locks on both instructions and data.

Note that flash clearing is the only way to clear data locks without clearing instruction locks, or to

clear instruction locks without clearing data locks. All instructions and snoop transactions that

clear locks clear both data and instruction locks.

7.7.6

Locks with Stale Data

If data is locked in the L2 and either the e500 core performs a cacheable copyback store or a dcbtst

misses in the L1, the L2 invalidates the line; however, the L2 clears the valid bit for the data, the

lock remains, and the line cannot be victimized. If the e500 core casts out modified data or pushes

it in response to a non-flush snoop, the L2 updates the data and sets the valid bit again, maintaining

the lock and keeping the data in the cache hierarchy.

7.8

PLRU L2 Replacement Policy

Line replacement is determined using a pseudo least-recently-used (PLRU) algorithm. There is a

valid bit (V0–V7) for each line. To determine the replacement victim (the line to be cast out), there

are seven PLRU bits (P0–P6) for each set. PLRU bits are updated every time a new line is allocated

or replaced and every time a line is modified or invalidated. There are two sets of lock bits, one

for instructions (I0–I7) and one for data (D0–D7) for every line. The lock bits act as a mask over

the PLRU bits to determine victim selection. The PLRU bits are updated regardless of line locking.

Figure 7-23 shows the binary decision tree used to generate the victim line. The eight ways of the

L2 cache are labeled W0–W7; the seven PLRU bits are labeled P0–P6.

MPC8540 Datasheet(PDF) 331 Page - Freescale Semiconductor, Inc