MPC8540 datasheet(328/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

7-24

Freescale Semiconductor

L2 Look-Aside Cache/SRAM

•

The L2 cache supports burst writes that lock an L2 cache line from peripheral devices or

from I/O controllers through write transactions with addresses that hit in a programmed

memory range that has the lock attribute set.

•

The L2 cache supports burst writes that allocate and/or lock an L2 cache line from

peripheral devices or I/O controllers through a write allocate transaction. See the system

logic programming model (for example, that of the DMA controller) for details on how to

set the transaction type for cache external writes to the L2.

7.6.2

Memory-Mapped SRAM Coherency Rules

Memory-mapped SRAM coherency rules are as follows:

•

External (non–core-initiated) accesses to memory-mapped SRAM must be marked

coherency-required. External accesses marked coherency-not-required to memory-mapped

SRAM may cause an address unavailable error.

•

Accesses to memory-mapped SRAM are cacheable only in the corresponding e500 L1

caches. External accesses must be marked cache-inhibited or be performed with

non-caching transactions.

7.7

L2 Cache Locking

The MPC8540 caches can be locked and cleared using the following methods:

•

Cache locking methods

— Individual line locks are set and cleared by using instructions defined by the e500 cache

locking APU, which is part of the Freescale Book E Implementation Standards (EIS).

These instructions include Data Cache Block Touch and Lock Set (dcbtls), Data Cache

Block Touch for Store and Lock Set (dcbtstls), and Instruction Cache Block Touch and

Lock Set (icbtls). For detailed information about these instructions, see the PowerPC

e500 Core Reference Manual.

— A lock attribute can be attached to write operations.

— Individual line locks are set and cleared through core-initiated instructions, by external

reads or writes, or by accesses to programmed memory ranges defined in L2 cache

external write address registers (L2CEWARn).

— The entire cache can be locked by setting configuration registers appropriately.

•

Methods for clearing locks

— Individual locks are cleared by cache locking APU instructions (Instruction Cache

Block Lock Clear (icblc) and Data Cache Block Lock Clear (dcblc)) or by snooped

flush unless the entire cache is locked.

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