MPC8540 datasheet(335/1302 Pages) FREESCALE

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L2 Cache Operation

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

7-31

Note that if the L2 SRAM is disabled, the L2 initial and final states are always I and the L2 never

hits. Similarly, if the L2 SRAM is in full memory-mapped SRAM mode, the L2 initial and final

states are always I and the L2 never hits for addresses not in the memory-mapped SRAM address

range. The L2 always hits for addresses in the enabled memory-mapped SRAM address ranges.

Table 7-22. State Transitions Due to Core-Initiated Transactions

Source of Transaction

Initial States

Hit

Final States

Comments

Cacheable instruction fetch

icbtls_L1

iL1

I/T

I/V

Same

L2CTL[L2DO] = 1. L2 touch instructions not

allocated in L1

I/V

L2CTL[L2DO] = 0

icbt_L2

dL1

I,E

E/EL

Yes

I/V

Same

I/V

L2CTL[L2DO] = 0. Restore locked line in L2 with

valid data from bus

icbtls_L2

dL1

I,E

I/T

Same

L2CTL[L2DO] = 1

Yes

L2CTL[L2DO] = 1

Yes

L2CTL[L2DO] = 1

L2CTL[L2DO] = 0

Yes

L2CTL[L2DO] = 0

Yes

Same

L2CTL[L2DO] = 0

L2CTL[L2DO] = 0. Restore locked line in L2 with

valid data from bus

Cache-inhibited instruction

fetch

N/A

No L1/L2 effect

Cacheable load (4-state)

Cacheable lwarx (4-state)

dcbt_L1 (4-state)

dcbtls_L1 (4-state)

dL1

I/T

Same

L2CTL[L2IO] = 1

Yes

L2CTL[L2IO] = 1

Yes

L2CTL[L2IO] = 1

L2CTL[L2IO] = 0

E/EL

Yes

Same

L2CTL[L2IO] = 0

L2CTL[L2IO] = 0. Restore locked line in L2 with

valid data from bus

Cache-inhibited load

N/A

No L1/L2 effect

Cache-inhibited lwarx

N/A

No L2 effect

Writeback Store

dL1

I/T

Same

L2 allocates when a line is cast out of L1.

EYes

Yes

Writeback stwcx.

dL1

I/T

Same

EYes

Yes

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