MPC8540 datasheet(339/1302 Pages) FREESCALE

339 / 1302 page

Initialization/Application Information

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

7-35

7.10.1 Initialization

This section describes L1 cache and memory-mapped SRAM initialization.

7.10.1.1 L2 Cache Initialization

After power-on reset, the valid bits in the L2 cache status array are in random states. Therefore, it

is necessary to perform a flash invalidate operation before using the array as an L2 cache. This is

done by writing a 1 to the L2I bit of the L2 control register (L2CTL). This can be done before or

simultaneously with the write that enables the L2 cache. That is, the L2E and L2I bits of L2CTL

can be set simultaneously. The L2I bit clears automatically, so no further writes are necessary.

7.10.1.2 Memory-Mapped SRAM Initialization

After power-on reset, the contents of the data and ECC arrays and are random, so all SRAM data

must be initialized before it is read. If the cache is initialized by the core or any other device that

uses sub-cacheline transactions, ECC error checking should be disabled during the initialization

process to avoid false ECC errors generated during the read-modify-write process used for

sub-cacheline writes to the SRAM array. This is done by setting the multi- and single-bit ECC

error disable bits of the L2 error disable register (L2ERRDIS[MBECCDIS, SBECCDIS]). See

Section 7.3.1.5.2, “Error Control and Capture Registers”. If the array is initialized by a DMA

engine using cache-line writes, then ECC checking can remain enabled during the initialization

process.

7.10.2 Managing Errors

This section describes recommended handling for ECC and tag parity errors.

7.10.2.1 ECC Errors

An individual soft error that causes a single- or mulit-bit ECC error can be cleared from the L2

array simply by executing a dcbf instruction for the address captured in the L2ERRADDR

performed again, the data will be re-allocated into the L2 with ECC bits set properly again.

If the threshold for single bit errors set in the L2ERRCTL register is exceeded, then the L2 cache

should be flash invalidated to clear out all single-bit errors.

Note that no data is lost by executing dcbf instructions or flash invalidate operations because the

L2 cache is write-through and contains no modified data.

MPC8540 Datasheet(PDF) 339 Page - Freescale Semiconductor, Inc