MPC8540 datasheet(342/1302 Pages) FREESCALE

342 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

III-2

Freescale Semiconductor

memory controller is responsible for controlling eight memory banks shared by a high

performance SDRAM machine, a general-purpose chip-select machine (GPCM), and up to

three user-programmable machines (UPMs). As such, it supports a minimal glue logic

interface to synchronous DRAM (SDRAM), SRAM, EPROM, flash EPROM, burstable

RAM, regular DRAM devices, extended data output DRAM devices, and other peripherals.

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Chapter 14, “Three-Speed Ethernet Controllers,” describes the two three-speed Ethernet

controllers on the MPC8540. These controllers provide 10/100/1Gb Ethernet support with

a complete set of media-independent interface options including GMII, RGMII, TBI, and

RTBI. Each controller provides very high throughput using a captive DMA channel and

direct connection to the MPC8540 memory coherency module.

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Chapter 15, “DMA Controller,” describes the four-channel general-purpose DMA

controller of the MPC8540. The DMA controller transfers blocks of data, independent of

the e500 core or external hosts. Data movement occurs among RapidIO and the local

address space. The DMA controller has four high-speed channels. Both the e500 core and

external masters can initiate a DMA transfer. All channels are capable of complex data

movement and advanced transaction chaining.

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Chapter 16, “PCI/PCI-X Bus Interface,” describes the PCI/PCI-X controller of the

MPC8540.

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Chapter 17, “RapidIO Interface,” describes the RapidIO controller of the MPC8540.

MPC8540 Datasheet(PDF) 342 Page - Freescale Semiconductor, Inc