MPC8540 datasheet(345/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

8-3

8.2.1

This section consists of detailed descriptions of those registers summarized in Table 8-1. Note that

these registers are shown in big-endian format.

8.2.1.1

ECM CCB Address Configuration Register (EEBACR)

The ECM CCB address configuration register, shown in Figure 8-2, controls arbitration and

streaming policies for the CCB.

Figure 8-2. ECM CCB Address Configuration Register (EEBACR)

Table 8-2 describes the EEBACR fields.

Table 8-1. ECM Memory Map

Local Memory Offset

Acces

Reset

Section/Pag

0x0_1000

EEBACR—ECM CCB address configuration register

R/W

0x0000_000

8.2.1.1/8-3

0x0_1010

EEBPCR—ECM CCB port configuration register

R/W

0x0n00_000

8.2.1.2/8-4

0x0_1E00

EEDR—ECM error detect register

Special 0x0000_000

8.2.1.3/8-5

0x0_1E08

EEER—ECM error enable register

R/W

0x0000_000

8.2.1.4/8-6

0x0_1E0C

EEATR—ECM error attributes capture register

0x0000_000

8.2.1.5/8-7

0x0_1E10

EEADR—ECM error address capture register

0x0000_000

8.2.1.6/8-8

027

A_STRM_DIS CORE_STRM_DIS A_STRM_CNT

Reset

0000_0000_0000_0000_0000_0000_0000_0011

Offset

0x0_1000

Table 8-2. EEBACR Field Descriptions

Bits

Name

Description

0–27

—

Reserved

A_STRM_DIS

Controls whether the ECM allows any streaming to occur.

0 Streaming is enabled.

1 Streaming is disabled.

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