MPC8540 datasheet(349/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

8-7

Table 8-5 describes EEER fields.

8.2.1.5

ECM Error Attributes Capture Register (EEATR)

The ECM error attributes capture register (EEATR) is shown in Figure 8-6.

Figure 8-6. ECM Error Attributes Capture Register (EEATR)

Table 8-6 describes EEATR fields.

Table 8-5. EEER Field Descriptions

Bits

Name

Description

0–30

—

Reserved

LAEE Local access error enable. Note that a read that attempts to access an unmapped target causes the

assertion of core_fault_in, which causes the core to generate a machine check interrupt, unless it is

disabled (by clearing HID1[RFXE]). If RFXE is zero and this error occurs, LAEE must be set to ensure

that an interrupt is generated. For more information, see Section 6.10.2, “Hardware

Implementation-Dependent Register 1 (HID1).”

0 Disable reporting local access errors as interrupts.

1 Enable reporting local access errors as interrupts.

10 11

15 16 17

20 21

BYTE_CNT

SRC_ID

TTYPE

VAL

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x0_1E0C

Table 8-6. EEATR Field Descriptions

Bits

Name

Description

0–2

—

Reserved

3–7

BYTE_CNT Byte count. Specifies the transaction byte count.

00000 32 bytes

00001 1 byte

00010 2 bytes

00011

3 bytes

00100 4 bytes

01000 8 bytes

10000 16 bytes

8–10

—

Reserved

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