MPC8540 datasheet(352/1302 Pages) FREESCALE

352 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

8-10

Freescale Semiconductor

e500 Coherency Module

ECM enforces coherency, snooping those transactions on the CCB, and taking castouts from the

e500 core as is necessary.

8.3.4

Global Data Multiplexor

Figure 8-1 shows how the global data multiplexor takes data bus connections and multiplexes

them onto one 128-bit global data bus. The global data mux allows initiators of write transactions

to route data to their targets and read targets to return data to the initiators.

8.3.5

CCB Interface

Figure 8-1 shows the CCB interface for both CCB address and data tenures. This interface formats

CCB address tenures for the ECM transaction queue. It also contains the queueing and buffering

needed to manage outstanding CCB data tenures. The buffers receive e500 core-initiated write and

I/O-initiated read data (that hit in the L2/SRAM module) from the e500 write (128-bit wide) and

read (128-bit wide) data buses and route them through the global data mux to the global data bus.

The buffers also receive e500 core-initiated read and I/O-initiated write data (that hit in the

L2/SRAM module) from the global data bus and forward them onto the CCB data bus (64 bits).

8.4

Initialization/Application Information

If the e500 core is used to initialize the MPC8540, the CPU boot configuration power-on reset pin

should be pulled high to initially set EEBPCR[CPU_EN]. See Chapter 4, “Reset, Clocking, and

Initialization,” for more information on power-up reset initialization.

If any device other than the e500 core, such as the boot sequencer or PCI, is used to initialize the

MPC8540, the CPU boot configuration power-on reset pin should be pulled low to initially clear

EEBPCR[CPU_EN]. This prevents the e500 core from accessing any configuration registers or

local memory space during initialization. However, in any such system, one step near the end of

the initialization routine must set EEBPCR[CPU_EN] to re-enable the e500 core. Note that for

basic functionality, EEBPCR[CPU_EN] is the only field that must be written (provided a device

other than the e500 core is used to initialize the device) in the ECM.

EEBPCR[CPU_PRI] specifies the priority level associated with all e500 core initiated

transactions. This value allows users running time-critical applications to adjust the average

response latency of transactions initiated by the core compared to those initiated by I/O masters.

This priority level affects whether the e500 core requests can interrupt the streaming of address

tenures initiated by (the ECM on behalf of) I/O masters. Only transactions with a priority greater

than the current CCB transaction can interrupt streaming. The higher the core’s priority, the lower

the average latency needed for it to obtain bus grants from the ECM, because it can interrupt lower

priority streaming. The default value of zero gives all core-initiated transactions the lowest

priority, which prevents the core from interrupting I/O master transaction streams.

MPC8540 Datasheet(PDF) 352 Page - Freescale Semiconductor, Inc