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MPC8540 Datasheet(PDF) 348 Page - Freescale Semiconductor, Inc

Part # MPC8540
Description  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 348 Page - Freescale Semiconductor, Inc

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
8-6
Freescale Semiconductor
e500 Coherency Module
Table 8-4 describes EEDR fields.
8.2.1.4
ECM Error Enable Register (EEER)
The ECM error enable register (EEER) shown in Figure 8-5 enables the reporting of error
conditions to the e500 core through the internal int interrupt signal.
Figure 8-5. ECM Error Enable Register (EEER)
Table 8-4. EEDR Field Descriptions
Bits
Name
Description
0
MULT_ERR Multiple error. Indicates the occurrence of multiple errors of the same type. Write one to clear.
0 Multiple errors of the same type were not detected.
1 Multiple errors of the same type were detected.
1–30
—
Reserved
31
LAE
Local access error. Write one to clear. Three cases can generate LAEs:
• Transaction does not map to any target. In this case the ECM injects read responses (with the
corrupt attribute set) and write data is dropped. Note that a read that attempts to access an
unmapped target causes the assertion of core_fault_in, which causes the core to generate a
machine check interrupt, unless it is disabled (by clearing HID1[RFXE]). If RFXE is zero and
this error occurs, EEER[LAEE] must be set to ensure that an interrupt is generated. For more
information, see Section 6.10.2, “Hardware Implementation-Dependent Register 1 (HID1).”
• Source and target IDs indicate that an OCN port initiated a transaction that targets an OCN
port. This loopback behavior can result from programming errors where inbound ATMU
window targets are inconsistent with targets configured in the local access windows for a given
address range. For this type of LAE, the dispatch (to OCN target in this case) is not screened
off; the LAE error is reported, but the transaction is still sent to its OCN target.
• Inbound read atomic set, clear, inc, or dec transactions from RapidIO target an interface other
than DDR (only the DDR supports these transactions). This condition screens off the dispatch
to the target (if one is mapped); the ECM injects read responses (with the corrupt attribute set)
and write data is dropped.
0 Local access error has not occurred.
1 Local access error occurred.
0
30
31
R
LAEE
W
Reset
0000_0000_0000_0000_0000_0000_0000_0000
Offset
0x0_1E08



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