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MPC8540 Datasheet(PDF) 347 Page - Freescale Semiconductor, Inc

Part # MPC8540
Description  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 347 Page - Freescale Semiconductor, Inc

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Memory Map/Register Definition
MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
Freescale Semiconductor
8-5
8.2.1.3
ECM Error Detect Register (EEDR)
The ECM error detect register (EEDR) is shown in Figure 8-4.
Figure 8-4. ECM Error Detect Register (EEDR)
8–29
—
Reserved
30–31
CPU_PRI Specifies the priority level of the e500 core (CPU) port. This priority level is used to determine
whether a particular port’s bus request can cause the CCB arbiter to terminate another port’s
streaming of address tenures.
00 Lowest priority level
01 Second lowest priority level
10 Highest priority level
11 Reserved
01
30
31
R
MULT_ERR
LAE
W
Reset
0000_0000_0000_0000_0000_0000_0000_0000
Offset
0x0_1E00
Table 8-3. EEBPCR Field Descriptions (continued)
Bits
Name
Description



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