MPC8540 datasheet(351/1302 Pages) FREESCALE

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Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

8-9

8.3

Functional Description

The following is a very general discussion of ECM operation.

8.3.1

I/O Arbiter

Figure 8-1 shows the I/O arbiter block that manages I/O-initiated address tenure requests arriving

on the request buses. Four request buses compete for access to the ECM, which can only process

one request at a time. The ECM uses two factors to select the winning request bus: the primary

factor is request priority and the secondary factor is longest waiting/least recently granted status.

By default all requesters use the lowest priority (priority 0) for requests. The TSEC controllers

dynamically raise and lower their priority levels based on FIFO depth. A starvation avoidance

algorithm prevents high priority requests from indefinitely starving low priority requesters. The

transaction from the winning request bus competes with e500 core requests for the CCB and entry

into the transaction queue.

8.3.2

CCB Arbiter

Figure 8-1 shows the CCB arbiter block coordinating the entry of new transactions into the ECM’s

transaction queue. It handles arbitration for requests to use the CCB from the e500 core and the

winning request bus and consequently controls when these new transactions can enter the

transaction queue.

Because the CCB bus operates most efficiently when it streams commands from one initiator, the

CCB arbiter alternates grants between streams of transactions from the processor and from the

winner of the I/O arbiter. The length of a stream (number of back-to-back transactions) is limited

by the A_STRM_CNT field in the EEBACR register. However, the arbiter also uses the priority

of the requests to limit streaming. If the priority of a new request is higher than that of a stream in

progress, then the higher priority transaction will interrupt the other stream. The priority of e500

transactions is set by the CPU_PRI field in EEBPCR register.

8.3.3

Transaction Queue

The ECM’s transaction queue performs three basic functions: target mapping and dispatching,

enforcement of ordering, and enforcement of coherency. The address of each transaction is

compared against each local access window, and the transaction is then routed to the appropriate

target interface associated with the local access window that the address hits within. Even though

the CCB and ECM allow the pipelining of transactions, the address tenures of all transactions

issued from masters other than the e500 core (all I/O masters) are strictly ordered and are

dispatched to their target interfaces in the same order they are submitted. For those transactions

accessing address space marked as snoopable, or space that may be cached by the e500 core, the

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