MPC8540 datasheet(355/1302 Pages) FREESCALE

355 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

9-1

Chapter 9

DDR Memory Controller

9.1

Introduction

The fully programmable DDR SDRAM controller supports most first-generation JEDEC standard

×8 or ×16 DDR memories available, including buffered and unbuffered DIMMs. However, mixing

unbuffered and registered DIMMs in the same system is not supported. Built-in error checking and

correction (ECC) ensures very low bit-error rates for reliable high-frequency operation. Dynamic

power management and auto-precharge modes simplify memory system design. A large set of

special features, including DLL software override, crawl mode, and ECC error injection support

rapid system debug.

NOTE

In this chapter, the word ‘bank’ refers to a physical bank specified by

a chip select; ‘logical bank’ refers to one of the four sub-banks in each

SDRAM chip. A sub-bank is specified by the two least significant bits

(lsbs) of a bank address.

Figure 9-1 is a high-level block diagram of the DDR memory controller with its associated

interfaces. Section 9.5, “Functional Description,” contains detailed figures of the controller.

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