MPC8540 datasheet(356/1302 Pages) FREESCALE

356 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

9-2

Freescale Semiconductor

DDR Memory Controller

Figure 9-1. DDR Memory Controller Simplified Block Diagram

9.2

Features

The DDR memory controller includes these distinctive features:

•

Support for DDR SDRAM

•

64-/72-bit SDRAM data bus

•

Programmable settings for meeting all SDRAM timing parameters

•

The following SDRAM configurations are supported

— As many as four physical banks (chip selects), each bank independently addressable

— 64-Mbit to 1-Gbit devices with

×8/×16 data ports (no direct ×4 support)

— Unbuffered and registered DIMMs

•

Support for data mask signals and read-modify-write for sub-double word writes. Note that

read-modify-write sequence is only necessary when ECC is enabled.

•

Support for double-bit error detection and single-bit error correction ECC (8-bit check

word across 64-bit data)

Address from

DDR SDRAM

Data from

DDR SDRAM

Data Signals

RMW

ECC

Request from

Row

Physical Bank,

FIFO

SDRAM

Address

Open Row

Address

Data Qualifiers

Clocks

To Error

MA[0:14]

MBA[0:1]

MCS[0:3]

MCAS

MRAS

MWE

MDM[0:8]

MCKE[0:1]

MDQS[0:8]

MDQ[0:63]

MECC[0:7]

MCK[0:5]

MSYNC_OUT

MSYNC_IN

Decode

Control

Open

Logical Bank,

Row

Table

Control

DLL

Input

Staging

Queue

Memory Array

Memory Control

Master

SDRAM

Master

Management

MCK[0:5]

ECM

ECC

Delay chain

Error

Signals

SDRAM

Control

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