MPC8540 datasheet(357/1302 Pages) FREESCALE

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External Signal Descriptions

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

9-3

•

Two-entry input request queue

•

Open page management (dedicated entry for each logical bank)

•

Memory controller clock frequency of two times the SDRAM clock with support for sleep

power management

•

Support for error injection

9.2.1

Modes of Operation

The DDR memory controller supports the following modes:

•

Dynamic power management mode. The DDR memory controller can reduce power

consumption by negating the SDRAM CKE signal when no transactions are pending to the

SDRAM.

•

Auto-precharge mode. Clearing DDR_SDRAM_INTERVAL[BSTOPRE] causes the

memory controller to issue an auto precharge command with every read or write

transaction. Auto precharge mode can be enabled for separate chip selects by setting

CSn_CONFIG[AP_n_EN].

9.3

External Signal Descriptions

This section provides descriptions of the DDR memory controller’s external signals. It describes

each signal’s behavior when the signal is asserted or negated and when the signal is an input or an

output.

NOTE

A bar over a signal name indicates that the signal is active low, such

as AS (address strobe). Active-low signals are referred to as asserted

(active) when they are low and negated when they are high. Signals

that are not active low, such as NMI (nonmaskable interrupt), are

referred to as asserted when they are high and negated when they are

low.

9.3.1

Signals Overview

Memory controller signals are grouped as follows:

•

Memory interface signals

•

Clock signals

•

Debug signals

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