MPC8540 datasheet(361/1302 Pages) FREESCALE

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External Signal Descriptions

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

9-7

MRAS

Row address strobe. Active-low SDRAM address multiplexing signal. Asserted for activate

commands. In addition; used for mode register set commands and refresh commands.

State

Meaning

Asserted—Indicates that a valid SDRAM row address is on the address bus for read and

write transactions. See Table 9-28 for more information on the states required on

MRAS for various other SDRAM commands.

Negated—The row address is not guaranteed to be valid.

Timing Assertion/Negation—Timing is directed by the values described in Section 9.4.1.3, “DDR

SDRAM Timing Configuration 1 (TIMING_CFG_1).”

High impedance—MRAS is always driven unless the memory controller is idle.

MCS[0:3]

Chip select. Four chip selects supported by the memory controller.

State

Meaning

Asserted—Selects a physical SDRAM bank to perform a memory operation as described

in Section 9.4.1.1, “Chip Select Memory Bounds (CSn_BNDS),” and Section 9.4.1.2,

“Chip Select Configuration (CSn_CONFIG).” The DDR controller asserts one of the

MCS[0:3] signals to begin a memory cycle.

Negated—Indicates no SDRAM action during the current cycle

Timing Assertion/Negation—Asserted to signal any new transaction to the SDRAM. The

transaction must adhere to the timing constraints set in TIMING_CFG_1.

High impedance—Always driven unless the memory controller is disabled

MWE

Write enable. Asserted when a write transaction is issued to the SDRAM. This is also used for mode

registers set commands and precharge commands.

State

Meaning

Asserted—Indicates a memory write operation. See Table 9-28 for more information on the

states required on MWE for various other SDRAM commands.

Negated—Indicates a memory read operation

Timing Assertion/Negation—Similar timing as MRAS and MCAS. Used for write commands.

High impedance—MWE is always driven unless the memory controller is idle.

MDM[0:8]

DDR SDRAM data output mask. Masks unwanted bytes of data transferred during a burst write. They

are needed to support sub-burst-size transactions (such as single-byte writes) on SDRAM where all

I/O occurs in multi-byte bursts. MDM0 corresponds to the most significant byte (MSB); MDM7

corresponds to the LSB. MDM8 corresponds to the ECC byte. Table 9-25 shows byte lane encodings.

State

Meaning

Asserted—Prevents writing to DDR SDRAM. Asserted when data is written to DRAM if the

corresponding byte(s) should be masked for the write. Note that the MDMn signals

are active-high for the DDR controller. MDMn is part of the DDR command encoding.

Negated—Allows the corresponding byte to be read from or written to the SDRAM

Timing Assertion/Negation—Same timing as MDQx as outputs

High impedance—Always driven unless the memory controller is disabled

Table 9-3. Memory Interface Signals—Detailed Signal Descriptions (continued)

Signal(s)

I/O

Description

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