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External Signal Descriptions

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

9-5

9.3.2

Detailed Signal Descriptions

The following sections describe the DDR SDRAM controller input and output signals, the

meaning of their different states, and relative timing information for assertion and negation.

9.3.2.1

Memory Interface Signals

Table 9-3 describes the DDR controller memory interface signals.

Table 9-3. Memory Interface Signals—Detailed Signal Descriptions

Signal(s)

I/O

Description

MDQ[0:63]

I/O

Data bus. Both input and output signals on the DDR memory controller.

As outputs for the bidirectional data bus, these signals operate as described below.

State

Meaning

Asserted/Negated—Represent the value of data being driven by the DDR memory

controller.

Timing Assertion/Negation—Driven coincident with corresponding data strobes (MDQS) signal.

High-impedance—No READ or WRITE command is in progress; data is not being driven

by the memory controller or the DRAM.

As inputs for the bidirectional data bus, these signals operate as described below.

State

Meaning

Asserted/Negated—Represents the state of data being driven by the external DDR

SDRAMs.

Timing Assertion/Negation—The DDR DIMM drives data during a READ transaction.

High-impedance—No READ or WRITE command in progress; data is not being driven by

the memory controller or the DRAM.

MDQS[0:8]

I/O

Data strobes. Inputs with read data and as outputs with write data.

As outputs, the data strobes are driven by the DDR memory controller during a write transaction. The

memory controller always drives these signals low unless a read has been issued and incoming data

strobes are expected. This keeps the data strobes from floating high when there are no transactions

on the DRAM interface.

State

Meaning

Asserted/Negated—Driven high when positive capture data is transmitted/received and

driven low when negative capture data is transmitted/received. Centered in the data

“eye” for writes; coincident with the data eye for reads. Treated as a clock. Data is

valid when signals toggle. See Table 9-25 for byte lane assignments.

Timing Assertion/Negation—If a WRITE command is registered at clock edge n, data strobes at

the DRAM assert centered in the data “eye” on clock edge n + 1. See the JEDEC

DDR SDRAM specification for more information.

As inputs, the data strobes are driven by the external DDR SDRAMs during a read transaction. The

data strobes are used by the memory controller to synchronize data latching.

State

Meaning

Asserted/Negated—Driven high when positive capture data is transmitted/received and

driven low when negative capture data is transmitted/received. Centered in the data

“eye” for writes; coincident with the data eye for reads. Treated as a clock. Data is

valid when signals toggle. See Table 9-25 for byte lane assignments.

Timing Assertion/Negation—If a READ command is registered at clock edge n, and the latency is

programmed in TIMING_CFG_1[CASLAT] to be m clocks, data strobes at the DRAM

assert coincident with the data on clock edge n+ m. See the JEDEC DDR SDRAM

specification for more information.

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