MPC8540 datasheet(358/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

9-4

Freescale Semiconductor

DDR Memory Controller

Table 9-1 shows how DDR memory controller external signals are grouped. The MPC8540

Integrated Host Processor Hardware Specifications has a pinout diagram showing pin numbers.

It also lists all electrical and mechanical specifications.

Table 9-2 shows the memory address signal mappings.

Table 9-1. DDR Memory Interface Signal Summary

Name

Function/Description

Reset

I/O

MDQ[0:63]

Data bus

All zeros

I/O

MDQS[0:8]

Data strobes

All zeros

I/O

MECC[0:7]

Error checking and correcting

All zeros

I/O

MCAS

Column address strobe

One

MA[0:14]

Address bus

All zeros

MBA[0:1]

Logical bank address

All zeros

MCS[0:3]

Chip select

All ones

MWE

Write enable

One

MRAS

Row address strobe

One

MDM[0:8]

Data mask

All zeros

MCK[0:5]

DRAM clock outputs

All zeros

MCK[0:5]

DRAM clock outputs (complement)

All ones

MCKE[0:1]

DRAM clock enable

All zeros

MSYNC_IN

DRAM DLL synchronization in

Zero

MSYNC_OUT DRAM DLL synchronization out

One

MDVAL

Memory debug data valid

Zero

MSRCID[0:4]

Memory debug source ID

All zeros

Table 9-2. Memory Address Signal Mappings

Signal Name

(Outputs)

JEDEC DDR DIMM Signals (Inputs)

Signal Name

(Outputs)

JEDEC DDR DIMM Signals (Inputs)

SDRAM 168-Pin DIMM

msb

MA14

—

MA5

MA13

A13

MA4

MA12

A12

MA3

MA11

A11

MA2

MA10

A10(AP)

MA1

MA9

MA0

MA8

MBA1

BA1

MA7

lsb

MBA0

BA0

MA6

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