MPC8540 datasheet(360/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

9-6

Freescale Semiconductor

DDR Memory Controller

MECC[0:7]

I/O

Error checking and correcting codes. Input and output signals for the DDR controller’s bidirectional

ECC bus. MECC[0:5] function in both normal and debug modes.

As normal mode outputs the ECC signals represent the state of ECC driven by the DDR controller on

writes. As debug mode outputs MECC[0:5] provide source ID and data-valid information. See

Section 20.4.3.2, “Debug Information on ECC Pins,” for more details.

State

Meaning

Asserted/Negated—Represents the state of ECC being driven by the DDR controller on

writes.

Timing Assertion/Negation—Same timing as MDQ

High-impedance—Same timing as MDQ

As inputs, the ECC signals represent the state of ECC driven by the SDRAM devices on reads.

State

Meaning

Asserted/Negated—Represents the state of ECC being driven by the DDR SDRAMs on

reads.

Timing Assertion/Negation—Same timing as MDQ

High-impedance—Same timing as MDQ

MA[0:14]

Address bus. Memory controller outputs for the address to the DRAM. MA[0:14] carry 15 of the

address bits for the DDR memory interface corresponding to the row and column address bits. MA[0]

is the lsb of the address output from the memory controller.

State

Meaning

Asserted/Negated—Represents the address driven by the DDR memory controller.

Contains different portions of the address depending on the memory size and the

DRAM command being issued by the memory controller. SeeTable 9-27 for a

complete description of the mapping of these signals.

Timing Assertion/Negation—The address is always driven when the memory controller is active.

It is valid when a transaction is driven to DRAM (when MCSn is negated).

High-impedance—When the memory controller is idle.

MBA[0:1]

Logical bank address. Outputs that drive the logical (or internal) bank address pins of the SDRAM.

Each SDRAM supports four addressable logical sub-banks. Bit zero of the memory controller’s output

bank address must be connected to bit zero of the SDRAM’s input bank address. MBA[0] is asserted

during the mode register set command to specify the extended mode register.

State

Meaning

Asserted/Negated—Selects the DDR SDRAM logical (or internal) bank to be activated

during the row address phase and selects the SDRAM internal bank for the read or

write operation during the column address phase of the memory access. Table 9-27

describes the mapping of these signals in all cases.

Timing Assertion/Negation—Same timing as MAn

High-impedance—Same timing as MAn

MCAS

Column address strobe. Active-low SDRAM address multiplexing signal. MCAS is asserted for read

or write transactions and for mode register set, refresh, and precharge commands.

State

Meaning

Asserted—Indicates that a valid SDRAM column address is on the address bus for read

and write transactions. See Table 9-28 for more information on the states required on

MCAS for various other SDRAM commands.

Negated—The column address is not guaranteed to be valid.

Timing Assertion/Negation—Assertion and negation timing is directed by the values described in

Section 9.4.1.3, “DDR SDRAM Timing Configuration 1 (TIMING_CFG_1).”

High-impedance—MCAS is always driven unless the memory controller is idle.

Table 9-3. Memory Interface Signals—Detailed Signal Descriptions (continued)

Signal(s)

I/O

Description

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