MPC8540 datasheet(362/1302 Pages) FREESCALE

362 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

9-8

Freescale Semiconductor

DDR Memory Controller

9.3.2.2

Clock Interface Signals

Table 9-4 contains the detailed descriptions of the clock signals of the DDR controller.

9.3.2.3

Debug Signals

The debug signals MSRCID[0:4] and MDVAL have no function in normal DDR controller

operation. A detailed description of these signals can be found in Section 20.4.3, “DDR SDRAM

Interface Debug.”

Table 9-4. Clock Signals—Detailed Signal Descriptions

Signal(s)

Description

MCK[0:5],

MCK[0:5]

O DRAM clock outputs and their complements. See Section 9.5.4.1, “Clock Distribution.”

State

Meanin

Asserted/Negated—The JEDEC DDR SDRAM specifications require true and

complement clocks. A clock edge is seen by the SDRAM when the true and

complement cross.

Timing Assertion/Negation—Should be synchronized at the SDRAM with the internal clocks of

the MPC8540. This is done with the DLL.

MCKE[0:1]

O Clock enable. Two identical output signals (each hereafter referred to simply as MCKE) used as

the clock enable to one or more SDRAMs. MCKE can be negated to stop clocking the DDR

SDRAM. While this results in system power savings, the user is cautioned to disable SDRAM

clocking only when there are no transactions on the interface.

State

Meanin

Asserted—Clocking to the SDRAM is enabled.

Negated—Clocking to the SDRAM is disabled and the SDRAM should ignore signal

transitions on MCK or MCK. MCK/MCK are don’t cares while MCKE is negated.

Timing Assertion/Negation—Similar timing to MAn

High impedance—Always driven

MSYNC_IN

DRAM DLL synchronization input. The DLL uses this input from the feedback loop to synchronize

SDRAM clocks with the internal clocks of the MPC8540. See Section 9.5.4.1, “Clock Distribution.”

State

Meanin

Asserted/Negated—Toggles at the same frequency as the applied SDRAM clocks

(MCKx), but is not in phase with MCKn

Timing Assertion/Negation—This is used for locking the DLL.

MSYNC_OU

O DRAM DLL synchronization output. Output for the DLL feedback loop. See Section 9.5.4.1, “Clock

Distribution.”

State

Meanin

Asserted/Negated—See MSYNC_IN description

MPC8540 Datasheet(PDF) 362 Page - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 362 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL