MPC8540 datasheet(365/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

9-11

Table 9-7 describes the CSn_CONFIG register fields.

9.4.1.3

DDR SDRAM Timing Configuration 1 (TIMING_CFG_1)

DDR SDRAM timing configuration register 1, shown in Figure 9-4, sets the number of clock

cycles between various SDRAM control commands.

Table 9-7. CSn_CONFIG Field Descriptions

Bits

Name

Description

0CS_n_EN

Chip select n enable

0 Chip select n is not active.

1 Chip select n is active and assumes the state set in CSn_BNDS.

1–7

—

Reserved

AP_n_EN

Chip select n auto precharge enable

0 Chip select n is auto precharged only if global auto precharge mode is enabled

(DDR_SDRAM_INTERVAL[BSTOPRE] = 0).

1 Chip select n always issues an auto precharge for read and write transactions.

9–20

—

Reserved

21–23

ROW_BITS_CS_n

Number of row bits for SDRAM on chip select n

000 12 row bits

001 13 row bits

010 14 row bits

011–111 Reserved

24–28

—

Reserved

29–31

COL_BITS_CS_n

Number of column bits for SDRAM on chip select n

000 8 column bits

001 9 column bits

010 10 column bits

011 11 column bits

011–111 Reserved

11 1213

1516

19 20 21

2324

28 29

PRETOACT ACTTOPRE

ACTTORW

CASLAT REFREC

WRREC

ACTTOACT

WRTORD

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x0_2108

Figure 9-4. DDR SDRAM Timing Configuration Register 1 (TIMING_CFG_1)

MPC8540 Datasheet(PDF) 365 Page - Freescale Semiconductor, Inc

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