MPC8540 datasheet(368/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

9-14

Freescale Semiconductor

DDR Memory Controller

9.4.1.5

DDR SDRAM Control Configuration (DDR_SDRAM_CFG)

The DDR SDRAM control configuration register, shown in Figure 9-6, enables the interface logic

and specifies certain operating features such as self refreshing, error checking and correcting,

registered DIMMS, and dynamic power management.

Figure 9-6. DDR SDRAM Control Configuration Register (DDR_SDRAM_CFG)

ACSM

Address and control shift mode

0 The DRAM address and control buses are output in the default mode.

1 The DRAM address and control buses are delayed by 1/2 DRAM cycle before being

driven onto the pins.

13–1

—

Reserved

19–2

WR_DATA_DELA

Write command to write data strobe timing adjustment. Controls the amount of delay

applied to the data and data strobes for writes.

000 0 clock delay

001 2/8 clock delay (recommended)

010 4/8 clock delay

011 6/8 clock delay

100 1 clock delay

101–111 Reserved

22–3

—

Reserved

MEM_EN

SREN

ECC_EN

RD_EN

0 0

SDRAM_TYPE

0 0

DYN_PWR

000

NCAP

Reset

0000_0010_0000_0000

2T_EN

0 00

00 0

0 0 0

0000_0000_0000_0000

Offset

0x0_2110

Table 9-9. TIMING_CFG_2 Register Field Descriptions (continued)

Bits

Name

Description

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