MPC8540 datasheet(371/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

9-17

Table 9-12 describes the DDR_SDRAM_INTERVAL fields.

9.4.1.8

Memory Data Path Error Injection Mask High

(DATA_ERR_INJECT_HI)

The memory data path error injection mask high register is shown in Figure 9-9.

Figure 9-9. Memory Data Path Error Injection Mask High Register (DATA_ERR_INJECT_HI)

Table 9-13 describes the DATA_ERR_INJECT_HI fields.

Table 9-12. DDR_SDRAM_INTERVAL Field Descriptions

Bits

Name

Description

0–1

—

Reserved

2–15

REFINT

Refresh interval. Represents the number of memory bus clock cycles between refresh cycles. One

row is refreshed in each DDR SDRAM physical bank during each refresh cycle. The value for

REFINT depends on the specific SDRAMs used and the interface clock frequency.

Note that REFINT must be set to a non-zero value in order for the DDR to enter sleep mode. See

Section 18.5.1.5.3, “Sleep Mode,” for additional details.

16–17

—

Reserved

18–31

BSTOPRE Precharge interval. Sets the duration (in memory bus clocks) that a page is retained after a DDR

SDRAM access. If BSTOPRE is zero, the DDR memory controller uses auto precharge read and

write commands rather than operating in page mode. This is called global auto precharge mode.

EIMH

Reset

0000_0000_0000_0000

Offset

0x0_2E00

Table 9-13. DATA_ERR_INJECT_HI Field Descriptions

Bits

Nam

Description

0–31 EIMH Error injection mask high data path. Used to test ECC by forcing errors on the high word of the data path.

Setting a bit causes the corresponding data path bit to be inverted on memory bus writes.

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