MPC8540 datasheet(370/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

9-16

Freescale Semiconductor

DDR Memory Controller

9.4.1.6

DDR SDRAM Mode Configuration (DDR_SDRAM_MODE)

The DDR SDRAM mode configuration register, shown in Figure 9-7, sets the values loaded into

the DDR’s mode registers.

Figure 9-7. DDR SDRAM Mode Configuration Register (DDR_SDRAM_MODE)

Table 9-11 describes the DDR_SDRAM_MODE fields.

9.4.1.7

DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL)

The DDR SDRAM interval configuration register, shown in Figure 9-8, sets the number of DRAM

clock cycles between bank refreshes issued to the DDR SDRAMs. In addition, the number of

DRAM cycles that a page is maintained after it is accessed is provided here.

015 16

ESDMODE

SDMODE

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x0_2118

Table 9-11. DDR_SDRAM_MODE Field Descriptions

Bits

Name

Description

0–15

ESDMOD

E[0:15]

Extended SDRAM mode. Specifies the initial value loaded into the DDR SDRAM extended mode

The value of ESDMODE[1:15] is driven onto MA[14:0] during the EXTENDED MODE REGISTER

SET operation of the intialization sequence. The lsb of ESDMODE (ESDMODE[15]) is driven onto

MA[0] and ESDMODE[1] is driven onto MA[14].

16–3

SDMODE

[0:15]

SDRAM mode. Specifies the initial value loaded into the DDR SDRAM mode register. The range

of legal values of legal values is specified by the DDR SDRAM manufacturer.

The value of SDMODE[1:15] is driven onto MA[14:0] during the MODE REGISTER SET

operation of the intialization sequence. The lsb of SDMODE (SDMODE[15]) is driven onto MA[0]

and SDMODE[1] is driven onto MA[14]. Because the memory controller forces SDMODE[3–8] to

certain values depending upon the state of the initialization sequence (for resetting the SDRAM’s

DLL) the corresponding bits of this field is ignored by the memory controller.

1516 1718

REFINT

BSTOPRE

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x0_2124

Figure 9-8. DDR SDRAM Interval Configuration Register (DDR_SDRAM_INTERVAL)

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