MPC8540 datasheet(369/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

9-15

Table 9-10 describes the DDR_SDRAM_CFG fields.

Table 9-10. DDR_SDRAM_CFG Field Descriptions

Bits

Name

Description

MEM_EN

DDR SDRAM interface logic enable

0 SDRAM interface logic is disabled

1 SDRAM interface logic is enabled. Must not be set until all other memory configuration

parameters have been appropriately configured by initialization code.

SREN

Self refresh enable (during sleep)

0 SDRAM self refresh is disabled during sleep or soft-stop. Whenever self-refresh is

disabled, the system is responsible for preserving the integrity of SDRAM during sleep or

soft-stop.

1 SDRAM self refresh is enabled during sleep or soft-stop

ECC_EN

ECC enable. Note that uncorrectable read errors may cause the assertion of core_fault_in,

which causes the core to generate a machine check interrupt unless it is disabled (by clearing

HID1[RFXE]). If RFXE is zero and this error occurs, ERR_DISABLE[MBED] must be zero and

ERR_INT_EN[MBEE] and ECC_EN must be one to ensure an interrupt is generated. See

Section 6.10.2, “Hardware Implementation-Dependent Register 1 (HID1).”

0 No ECC errors are reported. No ECC interrupts are generated.

1 ECC is enabled.

RD_EN

Registered DIMM enable. Specifies the type of DIMM used in the system.

0 Indicates unbuffered DIMMs.

1 Indicates registered DIMMs.

4–5

—

Reserved

6–7

SDRAM_TYPE Type of SDRAM device to be used

00–01 Reserved

10 DDR SDRAM

11 Reserved

8–9

—

Reserved

DYN_PWR

Dynamic power management mode

0 Dynamic power management mode is disabled.

1 Dynamic power management mode is enabled. If there is no ongoing memory activity, the

SDRAM CKE signal is negated.

11–13

—

Reserved

NCAP

Non-concurrent auto precharge

0 SDRAMs in system support concurrent auto precharge.

1 SDRAMs in system do not support concurrent auto precharge.

—

Reserved

2T_EN

2T timing enable

0 1T timing is used. The SDRAM command/address are held for only 1 cycle on the SDRAM

bus.

1 2T timing is enabled. The SDRAM command/address are held for 2 full cycles on the

SDRAM bus for every SDRAM transaction. However, the chip select is only held for the

second cycle.

17–31

—

Reserved

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