MPC8540 datasheet(367/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

9-13

9.4.1.4

DDR SDRAM Timing Configuration 2 (TIMING_CFG_2)

DDR SDRAM timing configuration 2, shown in Figure 9-5, sets the clock delay to data for writes.

Figure 9-5. DDR SDRAM Timing Configuration Register 2 (TIMING_CFG_2)

Table 9-9 describes the TIMING_CFG_2 fields.

25–27

ACTTOAC

Activate-to-activate interval ( t rrd). Number of clock cycles from an activate command until another

activate command is allowed for a different logical bank in the same physical bank (chip select).

000 Reserved

001 1 clock

010 2 clocks

011 3 clocks

100 4 clocks

101–111 Reserved

—

Reserved, should be cleared.

29–31

WRTORD

Last write data pair to read command issue interval (twtr). Number of clock cycles between the

last write data pair and the subsequent read command to the same physical bank.

000 Reserved

001 1 clock

010 2 clocks

011 3 clocks

100 4 clocks

101 5 clocks

110 6 clocks

111 7 clocks

R 0000

CPO

0000

ACSM

000000

WR_DATA_DELAY

0000000000

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x0_210C

Table 9-9. TIMING_CFG_2 Register Field Descriptions

Bits

Name

Description

0–3

—

Reserved

4–7

CPO

MCAS-to-preamble override. Defines the number of DRAM cycles between when a read

is issued and when the corresponding DQS preamble is valid for the memory controller.

0000 Default. MCAS to preamble is

defined as CASLAT + 1

0001

0010

+ 1/2

0011

+ 1

0100

+ 3/2

0101

+ 2

0110

+ 5/2

0111

+ 3

1000

+ 7/2

1001

+ 4

1010

+ 9/2

1011

+ 5

1100–1111 Reserved

8–11

—

Reserved

Table 9-8. TIMING_CFG_1 Field Descriptions (continued)

Bits

Name

Description

CASLAT

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