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MPC8540 Datasheet(PDF) 364 Page - Freescale Semiconductor, Inc

Part # MPC8540
Description  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 364 Page - Freescale Semiconductor, Inc

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
9-10
Freescale Semiconductor
DDR Memory Controller
9.4.1.1
Chip Select Memory Bounds (CSn_BNDS)
The chip select bounds registers (CSn_BNDS) shown in Figure 9-2 define the starting and ending
address of the memory space that corresponds to the individual chip selects. Note that the size
specified in CSn_BNDS should equal the size of physical DRAM. Also, note that EAn must be
greater than or equal to SAn. If the high-order 8 bits of an address are greater than or equal to SAn,
and they are less than or equal to EAn, then chip select n will be used.
Table 9-6 describes the CSn_BNDS register fields.
9.4.1.2
Chip Select Configuration (CSn_CONFIG)
The chip select configuration (CSn_CONFIG) registers shown in Figure 9-3 enable the DDR chip
selects and set the number of row and column bits used for each chip select. These registers should
be loaded with the correct number of row and column bits for each SDRAM. Because
CSn_CONFIG[ROW_BITS_CS_n,COL_BITS_CS_n] establish address multiplexing, the user
should take great care to set these values correctly.
07
8
15 16
23 24
31
R 0
0000000
SAn
0000
0000
EAn
W
Reset
0000_0000_0000_0000_0000_0000_0000_0000
Offset
0x0_2000, 0x0_2008, 0x0_2010, 0x0_2018
Figure 9-2. Chip Select Bounds Registers (CSn_BNDS)
Table 9-6. CSn_BNDS Field Descriptions
Bits
Name
Description
0–7
—
Reserved
8–15
SAn
Starting address for chip select (bank) n. This value is compared against the 8 msbs of the address.
16–23
—
Reserved
24–31
EAn
Ending address for chip select (bank) n. This value is compared against the 8 msbs of the address.
0
1
7
8
9
20 21
23 24
28 29
31
R
CS_n _EN
00 000 00
AP_n_EN
0 000 000 000 0 0
ROW_BITS_CS_n
00 0 0 0
COL_BITS_CS_n
W
Reset
0000_0000_0000_0000_0000_0000_0000_0000
Offset
0x0_2080, 0x0_2084, 0x0_2088, 0x0_208C
Figure 9-3. Chip Select Configuration Register (CSn_CONFIG)



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